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All Journal IAES International Journal of Robotics and Automation (IJRA)
Chumachenko, Svetlana
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Automotive Engineering Electrical & Electronics Engineering

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Vector synthesis of fault testing map for logic Hahanov, Vladimir; Gharibi, Wajeb; Chumachenko, Svetlana; Litvinova, Eugenia
IAES International Journal of Robotics and Automation (IJRA) Vol 13, No 3: September 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijra.v13i3.pp293-306

Abstract

Vector synthesis of fault testing (simulation) map for logic is proposed, which without simulation allows to determine of all faults detected on test sets, as well as determining test sets to detect specified faults. For synthesis, a superposition of smart data structures is used, containing: a deductive matrix D, as a derivative of the logical vector L, test truth table T, and fault truth table F. The deductive matrix is seen as the gene of functionality and base of fault simulation mechanism to solve all the problems of testing and verification. In the matrix synthesis, an axiom is used: all the mentioned tables are identical in shape to each other and always interact with each other convolutionally T⊕L⊕F=0. A universal deductive reversing converter “test-faults” and “faults-test” for logical functionalities of any dimension is proposed. Converter functions: fault simulation on test sets T→F and synthesis of test sets F→T to detect the specified faults. The converter can be used as a test generation and fault simulation service for IP-core system-on-chip (SoC) under the IEEE 1500 SECT standard. Based on the deductive matrix, a fault testing map for logic is built, where each test set is matched with the logic-detected faults of the input lines.
Faults-as-address simulation Hahanov, Vladimir; Chumachenko, Svetlana; Litvinova, Eugenia; Hahanov, Ivan; Ponomarova, Veronika; Khakhanova, Hanna; Kulak, Georgiy
IAES International Journal of Robotics and Automation (IJRA) Vol 13, No 4: December 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijra.v13i4.pp452-468

Abstract

Fault-as-address-simulation (FAAS) is a simulation mechanism for testing combinations of circuit line faults, represented by the bit addresses of element logical vectors. The XOR relationship between the test set T and the truth table L of the element forms a deductive vector for fault simulation, using truth table addresses or the logic vector bits. Addresses are used in the simulation matrix to mark those n-combinations of input faults detected at the element's output. The columns of the simulation matrix are treated as n-row addresses to generate an element output row via a deductive vector. There is no transport of input faults to the element output, Only the 1-signals written in the non-input row coordinates of the circuit simulation matrix. The simulation matrix is initially filled with 1-signals along the main diagonal. The line faults detected on the test set of circuits are determined by the inverse of lines good values, which have 1-values in the matrix row corresponding to the output circuit element. The deductive vector is obtained by the XOR-relations between the test set and logical vector in three table operations. The advantage of the proposed FAAS mechanism is the predictable complexity of the algorithm and memory consumption for storing data structures when simulating a test set.
Vector-logic computing for faults-as-address deductive simulation Gharibi, Wajeb; Hahanov, Vladimir; Chumachenko, Svetlana; Litvinova, Eugenia; Hahanov, Ivan; Hahanova, Irina
IAES International Journal of Robotics and Automation (IJRA) Vol 12, No 3: September 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijra.v12i3.pp274-288

Abstract

The aim of the research is to create logic-free vector computing, leveraging read-write transactions in memory, to solve the problems of modeling and simulation stuck-at-fault combinations for complex logic elements and digital structures. At the same time, the problem of creating smart data structures based on logical vectors, truth tables, and deductive matrices is considered to simplify algorithms for parallel stuck-at-fault simulation. Vector computing is a computational process based on read-write transactions on bits of a binary vector of functionality, where the input data and faults are the addresses of the bits. A method for the synthesis of deductive vectors for propagating input fault lists is proposed, which has a quadratic computational complexity of read-write transactions. Deductive vectors, combined into a quadratic matrix, represent explicit data structures for parallel simulation of single and multiple stuck-at-faults. The initial information for constructing a deductive matrix is a logical vector and a bit-recoding matrix. Matrix is easily obtained using a recursive procedure based on the combinatorial properties of the truth table. Considering emerging trends, focused on in-memory computing, an algorithm for fault, as addresses, simulation is proposed, using logical and deductive vectors placed in memory. The simulation algorithm is proposed not to use commands of powerful processors.
Co-Authors Hahanov, Ivan Hahanov, Vladimir Hahanova, Irina Khakhanova, Hanna Kulak, Georgiy Litvinova, Eugenia Ponomarova, Veronika Wajeb Gharibi, Wajeb