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All Journal International Journal of Electrical and Computer Engineering IAES International Journal of Artificial Intelligence (IJ-AI) Indonesian Journal of Electrical Engineering and Computer Science
Prasad, Sarappadi Narasimha
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Computer Science & IT Electrical & Electronics Engineering Engineering

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Photo-realistic photo synthesis using improved conditional generative adversarial networks Mandara Kirimanjeshwara, Raghavendra Shetty; Prasad, Sarappadi Narasimha
IAES International Journal of Artificial Intelligence (IJ-AI) Vol 13, No 1: March 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijai.v13.i1.pp516-523

Abstract

There are a wide range of potential uses for both the forward (generating face drawings from actual images) and backward (generating photos from synthetic face sketches). However, photo/sketch synthesis is still a difficult problem to solve because of the distinct differences between photos and sketches. Existing frameworks often struggle to acquire a strong mapping among the geometry of drawing and its corresponding photo-realistic pictures because of the little amount of paired sketch-photo training data available. In this study, we adopt the perspective that this is an image-to-image translation issue and investigate the usage of the well-known enhanced pix2pix generative adversarial networks (GANs) to generate high-quality photo-realistic pictures from drawings; we make use of three distinct datasets. While recent GAN-based approaches have shown promise in image translation, they still struggle to produce high-resolution, photorealistic pictures. This technique uses supervised learning to train the generator's hidden layers to produce low-resolution pictures initially, then uses the network's implicit refinement to produce high-resolution images. Extensive tests on three sketch-photo datasets (two publicly accessible and one we produced) are used to evaluate. Our solution outperforms existing image translation techniques by producing more photorealistic visuals with a peak signal-to-noise ratio of 59.85% and pixel accuracy of 82.7%. 
Sqrt-Loglogish CNN and Markov model for 5G spectrum sensing application Rajanna, Anupama; Kulkarni, Srimannarayana; Prasad, Sarappadi Narasimha
Indonesian Journal of Electrical Engineering and Computer Science Vol 35, No 3: September 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v35.i3.pp1480-1490

Abstract

The research presents innovative methods for spectrum sensing in 5G networks, using the Sqrt-Loglogish convolutional neural network (SL-CNN) and hidden orthogonal intuitionistic fuzzy Markov model (HOIFMM). The proposed methods aim to tackle issues related to detecting principal user signals accurately, mitigating interference, and efficiently utilizing the spectrum in wideband spectrum environments due to their diverse and ever changing characteristics. The Sqrt-Loglogish CNN improves spectrum sensing by addressing static threshold dependency and potential overfitting. The HOIFMM offers a complex framework for predicting sparsity levels and primary user patterns. The results highlight the effectiveness of the suggested techniques in differentiating primary user signals from noise and interference, resulting in enhanced interference management tactics and overall network performance. MATLAB simulation is performed and compared the proposed methods performance with existing state-of-the-art methods such as CNN, deep neural network (DNN), long short-term memory (LSTM) and artificial neural networks (ANN). The proposed method has outperformed existing methods in terms of sensitivity, accuracy, and precision. Future endeavors include improving these methods, investigating sophisticated machine learning algorithms, and doing real world validations to guarantee scalability and resilience in various 5G deployment situations. This research advances the spectrum sensing capabilities in 5G networks, potentially improving efficiency, reliability, and quality of service.
A robust penalty regression function-based deep convolutional neural network for accurate cardiac arrhythmia classification using electrocardiogram signals Pratima, Anniah; Kanathur, Gopalakrishna; Prasad, Sarappadi Narasimha
IAES International Journal of Artificial Intelligence (IJ-AI) Vol 14, No 1: February 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijai.v14.i1.pp629-640

Abstract

Cardiac arrhythmias are a leading cause of morbidity and mortality worldwide, necessitating accurate, and timely diagnosis. This paper presents a novel approach for the classification of cardiac arrhythmias using a penalty regression function (PRF)-based deep convolutional neural network (DCNN). The proposed model integrates advanced preprocessing techniques, including frechet with fitness rank distribution-based anas platyrhynchos optimization (FFRD-APO) for feature selection and ensemble empirical mode decomposition (EEMD) for signal decomposition. Utilizing the St. Petersburg INCART 12-lead arrhythmia database, the PRF-DCNN model achieved superior performance metrics: an area under the curve-receiver operating characteristic (AUC-ROC) of 0.97, accuracy of 0.95, precision of 0.93, recall of 0.92, specificity of 0.97, and an F1 score of 0.93. The PRF effectively mitigated overfitting, ensuring robust and reliable classification across varied patient demographics. The model demonstrated significant improvements over traditional methods, offering an efficient solution for real-time cardiac monitoring and diagnosis. This study underscores the potential of PRF-DCNN in enhancing automated arrhythmia detection and lays the groundwork for future research to optimize and validate this approach in diverse clinical settings.
Fault tolerant design for 8-bit Dadda multiplier for neural network applications Chandrasekharan, Raji; Prasad, Sarappadi Narasimha
International Journal of Electrical and Computer Engineering (IJECE) Vol 15, No 3: June 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v15i3.pp2697-2705

Abstract

As digital electronic systems continue to shrink in size, they face increased susceptibility to transient errors, especially in critical applications like neural networks, which are not inherently error-resilient. Multipliers, fundamental components of neural networks, must be both fault tolerant and efficient. However, traditional fault free designs consume excessive power and require substantial silicon real estate. Among existing multiplier architectures, the Dadda multiplier stands out for its speed and efficiency, but it lacks fault tolerance needed for robust neural network applications. Therefore, there is need to design a power efficient and fault free Dadda multiplier that can address these challenges without significantly increasing power consumption or hardware complexity. In this paper a solution involving a fault tolerant Dadda multiplier optimized for neural network applications is proposed. Because of its speed and efficiency when compared to other multipliers Dadda multiplier is used as the base architecture which is designed using carry select adder (CSA) in conjunction with binary to excess one converter to reduce power and complexity. To enhance fault tolerance, self-repairing full adder is used to implement the CSA. This allows the system to detect and correct errors, ensuring robust operation in the presence of transient faults. This combination achieves a power efficient, fault tolerant multiplier with a power consumption of 52.3 mW, reflecting a 3% reduction in power compared to existing designs.
Co-Authors Chandrasekharan, Raji Kanathur, Gopalakrishna Kulkarni, Srimannarayana Mandara Kirimanjeshwara, Raghavendra Shetty Pratima, Anniah Rajanna, Anupama