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All Journal IAES International Journal of Artificial Intelligence (IJ-AI)
Moharir, Minal
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Computer Science & IT Engineering

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Evaluation of genetic algorithm in network-on-chip based architecture Radha, Doraisamy; Moharir, Minal
IAES International Journal of Artificial Intelligence (IJ-AI) Vol 13, No 2: June 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijai.v13.i2.pp1479-1488

Abstract

An increase in the number of cores gives a significant bounce in performance than an improvement in any of the factors or hardware. Many core systems use network-on-chip (NoC) for efficient communications among the cores in the system. However, the problem with NoC-based communication is that it significantly consumes a large amount of power and energy because the number of routers increases with the increase in the number of cores in the system. Power consumed by such components leads to degradation of the performance. The placement of cores in the topology is non-deterministic polynomial-time hardness (NP-Hard) problem. The optimal placement of cores in NoC is essential as it minimizes latency and communication costs. Thus, the NP-Hard problem of placing cores is solved using genetic algorithm (GA) based quadtree topology. The proposed work shows the analysis of GA-based quadtree topology, which outperforms other topologies in most aspects. The performance evaluation of GA-based quadtree topology is based on latency, throughput, power, area, bisection bandwidth, and diameter. Comparing these parameters with other topologies shows the prominence of the quadtree topology. The evaluation is performed in the Booksim simulator, and the experimental results revealed that the proposed GA-based quad tree-based topology is efficient for NoC-based communications.
Performance analysis of congestion-aware Q-routing algorithm for network on chip Srivastava, Smriti; Moharir, Minal; Gunisetty, Shivaneetha
IAES International Journal of Artificial Intelligence (IJ-AI) Vol 13, No 1: March 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijai.v13.i1.pp798-806

Abstract

A network on chip’s performance is greatly impacted by network congestion due to the substantial increase in latency and energy utilized. Designing routing strategies that keep the network informed of the status of traffic is made easier by machine learning techniques. In this work, a reinforcement-based congestion-aware Q-routing (CAQR) technique has been presented. The proposed algorithm performed better in comparison to the conventional XY routing method tested against the SPEC CPU2006 benchmark suite in the gem5 NoC simulator tool. The suite used has 4 benchmarks, namely, namd, lbm, leslie3d and bzip2 which can be used for the cores in the network in any combination. The tests were run with 16 cores on a 44 network with the maximum instruction count supported by the system (here 5,000). The proposed Q-routing algorithm showed an average of 19% reduction for benchmark simulation as compared to the Dimension-ordered (X-Y) routing for readings of average packet latency which is a crucial factor in determining a network’s efficiency. The analysis also shows an average reduction of 24%, 10%, 23% and 47% in terms of average packet network latency, average flit latency, average flit network latency and average energy consumption across various benchmarks.
Co-Authors Gunisetty, Shivaneetha Radha, Doraisamy Srivastava, Smriti