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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Chaturvedi, Abhay
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Economics, Econometrics & Finance

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Role of tuning techniques in advancing the performance of negative capacitance field effecting based full adder Daniel, Ravuri; Prasad, Bode; Chaturvedi, Abhay; Balaswamy, Chinthaguntla; Sudarsa, Dorababu; Vinodhkumar, Nallathambi; Eamani, Ramakrishna Reddy; Sudhakar, Ambarapu; Rajanna, Bodapati Venkata
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 1: March 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i1.pp59-68

Abstract

The increasing demand for faster, robust, and efficient device development of enabling technology to mass production of industrial research in circuit design deals with challenges like size, efficiency, power, and scalability. This paper, presents a design and analysis of low power high speed full adder using negative capacitance field effecting transistors. A comprehensive study is performed with adiabatic logic and reversable logic. The performance of full adder is studied with metal oxide field effect transistor (MOSFET) and negative capacitance field effecting (NCFET). The NCFET based full adder offers a low power and high speed compared with conventional MOSFET. The complete design and analysis are performed using cadence virtuoso. The adiabatic logic offering low delay of 0.023 ns and reversable logic is offering low power of 7.19 mw.
Co-Authors Balaswamy, Chinthaguntla Daniel, Ravuri Eamani, Ramakrishna Reddy Prasad, Bode Rajanna, Bodapati Venkata Sudarsa, Dorababu Sudhakar, Ambarapu Vinodhkumar, Nallathambi