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P., Rajeswari
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Electrical & Electronics Engineering

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Journal : Bulletin of Electrical Engineering and Informatics

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Efficient k-way partitioning of very-large-scale integration circuits with evolutionary computation algorithms P., Rajeswari; Chandra S., Theodore; Sasi, Smitha
Bulletin of Electrical Engineering and Informatics Vol 13, No 6: December 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/eei.v13i6.5781

Abstract

The standardization of very-large-scale integration (VLSI) physical architecture for VLSI chips and multichip platforms is now in its early stages of development. The purpose of VLSI partitioning is to divide the circuit into numerous smaller circuits with few connections in between. Partitioning is the fundamental problem in circuit design and division. The efficient method of evolutionary computation may be used to tackle the partitioning problem in VLSI circuit design. It provides a heuristic approach to solve this problem by exploring the solution space and incrementally improving the quality of the solutions. In order to obtain the shortest wire length (WL), area, and connections, an evolutionary optimized simulated annealing memetic algorithm (OSAMA) that incorporates one or more local search phases inside its evolutionary cycle was developed.
Co-Authors Chandra S., Theodore Sasi, Smitha