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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES) Bulletin of Electrical Engineering and Informatics
Sasi, Smitha
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Economics, Econometrics & Finance Electrical & Electronics Engineering

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Efficient k-way partitioning of very-large-scale integration circuits with evolutionary computation algorithms P., Rajeswari; Chandra S., Theodore; Sasi, Smitha
Bulletin of Electrical Engineering and Informatics Vol 13, No 6: December 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/eei.v13i6.5781

Abstract

The standardization of very-large-scale integration (VLSI) physical architecture for VLSI chips and multichip platforms is now in its early stages of development. The purpose of VLSI partitioning is to divide the circuit into numerous smaller circuits with few connections in between. Partitioning is the fundamental problem in circuit design and division. The efficient method of evolutionary computation may be used to tackle the partitioning problem in VLSI circuit design. It provides a heuristic approach to solve this problem by exploring the solution space and incrementally improving the quality of the solutions. In order to obtain the shortest wire length (WL), area, and connections, an evolutionary optimized simulated annealing memetic algorithm (OSAMA) that incorporates one or more local search phases inside its evolutionary cycle was developed.
An optimized simulated annealing memetic algorithm for power and wirelength minimization in VLSI circuit partitioning Rajeswari, P.; Sasi, Smitha
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 2: July 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i2.pp365-374

Abstract

The development of physical architecture standards for very large scale integration (VLSI) single and multichip platforms is still in its early stages. To deal with the growing complexity of modern VLSI systems, it has become common practice to split large circuit architectures into smaller, easier-to-manage sub-circuits. Circuit partitioning improves parallel modeling, testing, and system performance by lowering chip size, number of components and interconnects, wire length (WL), and delays. VLSI partitioning's primary goal is to split a circuit into smaller blocks with as few connections as possible between them. This is frequently accomplished by recursive bi-partitioning until the required complexity level is reached. Thus, partitioning is a fundamental circuit design challenge. An efficient remedy that offers a heuristic method that explores the design space to iteratively enhance outcomes is evolutionary computation. In order to minimize WL, area, and interconnections, we provide an optimized simulated annealing memetic algorithm (OSAMA) that combines local search methods with evolutionary tactics. The efficiency of the method was evaluated using criteria like runtime, cost, delay, area, and WL. OSAMA's ability for effective partitioning is demonstrated by experimental results, which confirm that it dramatically lowers important design parameters in VLSI circuits.
Co-Authors Chandra S., Theodore P., Rajeswari Rajeswari, P.