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Rao, Surampudi Srinivasa
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Design of energy efficient and reconfigurable sample rate converter using FPGA devices Pinjerla, Swetha; Rao, Surampudi Srinivasa; Reddy, Puttha Chandrasekhar
Indonesian Journal of Electrical Engineering and Computer Science Vol 36, No 2: November 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v36.i2.pp854-862

Abstract

The technique of sampling rate conversion is frequently employed in various fields. A discrete time-varying filter, as well as a sample skip or sample duplicate operation, are required for the most general instance of an irrational and time-variable conversion factor. A wide band of signals is employed in a communication system, especially in specific situations where data must be transferred directly. A broadband sample rate converter with changeable filter parameters is necessary in such cases. Sample rate conversion is a communication system technology that accepts a band-limited high sample rate modulated signal and uses filtering to retrieve the original message signal. In this work, an energy-efficient implementation of a reconfigurable field programmable gate arrays (FPGA) architecture for a sample rate converter is proposed. In applications such as multi-rate signal processing and the construction of channelized receivers, sample rate conversion is used. In this work, a new FPGA based design is proposed to perform multiple sample rate conversion for various data transmission protocols such as Wi-Fi, ZigBee and Bluetooth. A lowpass filter with a 2.45 GHz filter with the minimum number of taps is used to avoid the aliasing effect. Xilinx synthesis tools are used to estimate hardware resource utilization and speed analyses. XC6VCX240t-2FF484 FPGA achieves 15% hardware resource occupancy at a maximum clock speed of 133 MHz.
Co-Authors Pinjerla, Swetha Reddy, Puttha Chandrasekhar