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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Marouthu, Anusha
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Economics, Econometrics & Finance

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Performance analysis of parallel prefix adders developed with field programmable gate array technology Mahammad, Masood Ahmad; Uppala, Appala Raju; Prasad, Suggala Ram; Marouthu, Anusha
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp109-116

Abstract

In many digital systems like high-performance computing and digital signal processing, parallel prefix adders are vital. Field programmable gate array (FPGA) technology is a well-known platform for developing parallel prefix adders. FPGA performance depends on bit size of the adder, the adder structure chosen, and the implementation specifications. An examination of the performance and area of parallel prefix adders developed using FPGA technology is presented in this research work. We look into how different design factors, such as the adder structure and the number of input bits, affect the performance and area of parallel prefix adders. The different adders used are Sklansky, Kogge-Stone, Brent-Kung, Han-Carlson, and Ladner-Fisher adders. These adders are implemented using Verilog hardware description language (Verilog HDL) on FPGA boards. The performance is significantly influenced by choice of adder structure and design factors optimized for area or performance. The suggestions for choosing the best adder structure and design factors for the best performance or optimized area are obtained from the synthesis results. Ladner-Fisher adders is best parallel prefix adder with respect area and performance compared with the Sklansky, Kogge-Stone, Brent-Kung and Han-Carlson. Our synthesis can be used as a guide for designers looking to construct specific hardware on FPGA.
FPGA implementation of high-performance Huffman encoder for image processing applications Ahmad Mahammad, Masood; Raju Uppala, Appala; Mazhar Hussain, Shaik; Marouthu, Anusha
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 1: March 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i1.pp68-77

Abstract

An optimized Huffman encoder is essential in all applications where it is necessary to achieve the best performance, such as audio coding, data encryption, data compression, and image processing applications. This article presents a space-optimized encoding scheme to maximize performance and minimize latency in Dual Huffman encoding. The proposed approach employs dynamic tree selection using Dual Huffman encoding. A Dual Huffman code with dynamic tree selection can be run in parallel to support high-throughput applications. The resulting design optimally creates the Huffman dual encoding. This codeword table is based on a dynamic tree generation and selection algorithm, leading to a faster encoding process with lower latency. The architecture was developed using Vivado Xilinx 2023.2 and tested on three different field programmable gate array (FPGA) platforms (Zynq 7045, Zynq 7100, and Kria KV260 AI Vision board). A performance comparison between devices demonstrates that the Kria KV260 had the lowest latency (100 ns), as opposed to the Zync 7045 and Zynq 7100, which had latencies of 200 ns and 150 ns, respectively. These results elucidate the scalability of the architecture and its suitability for real-time image compression. When implemented on the Kria KV260, the dynamic tree selection-based Dual Huffman encoder is capable of fast, parallel image compression. The compression makes it a good candidate for advanced FPGA-based image processing systems with internet of things (IoT) applications.
Co-Authors Ahmad Mahammad, Masood Mahammad, Masood Ahmad Mazhar Hussain, Shaik Prasad, Suggala Ram Raju Uppala, Appala Uppala, Appala Raju