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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES) International Journal of Applied Power Engineering (IJAPE)
Potladurty, Suresh Babu
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Economics, Econometrics & Finance Electrical & Electronics Engineering

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Optimal distributed generator placement for loss reduction using fuzzy and adaptive grey wolf algorithm Sarika, Daruru; Babu, Palepu Suresh; Gopi, Pasala; Reddy, Manubolu Damodar; Potladurty, Suresh Babu
International Journal of Applied Power Engineering (IJAPE) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijape.v14.i1.pp155-162

Abstract

This research provides a new methodology for locating distributed generation (DG) units in distribution electrical networks utilizing the fuzzy and adaptive grey wolf optimization algorithm (AGWOA) to decrease power losses and enhance the voltage profile. Everyday living relies heavily on electrical energy. The promotion of generating electrical power from renewable energy sources such as wind, tidal wave, and solar energy has arisen due to the significant value placed on all prospective energy sources capable of producing it. There has been substantial research on integrating distributed generation into the electricity system due to the growing interest in renewable sources in recent years. The primary reason for adding distributed generation sources for the network is to supply a net quantity of power, lowering power losses. Determining the amount and location of local generation is crucial for reducing the line losses of power systems. Numerous studies have been conducted to determine the best location for distributed generation. In this study, DG unit placement is determined using a fuzzy technique. In contrast, photovoltaic (PV) and capacitor placement and size are determined simultaneously using an adaptive grey wolf technique based on the cunning behavior of wolves. The proposed method is developed using the MATLAB programming language; the results are then provided after testing on test systems with 33-bus and 15-bus.
Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications Venkata Sudhakar, Chowdam; Potladurty, Suresh Babu; Karipireddy, Prasad Reddy
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 2: July 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i2.pp398-411

Abstract

The multiplier is an essential component in real-time applications. Even though approximation arithmetic affects output accuracy in multipliers, it offers a realistic avenue to constructing power area and speed-efficient digital circuits. The approximation computing technique is commonly used in error-tolerant applications such as signal, image, and video processing. In this paper, approximate multipliers (AMs) are designed using both conventional and approximate half adders (A-HA) and full adders (A-FA), which are strategically placed to add partial products at the most significant bit (MSB) positions, and OR gates are used to add partial products at the lower significant bit (LSB). In addition, this research article demonstrates unsigned and signed multipliers using the ripple carry adder (RCA), carry save adder (CSA), conditional sum adder (COSA), carry select adder (CSLA), and clock gating technique. The proposed multipliers are implemented in Verilog hardware description language (HDL) and simulated on the Xilinx VIVADO 2021.2 design tool with target platform Artix-7 AC701 FPGA. The simulation results found that unsigned and signed approximate multiplier power consumption was reduced by 13% and 18.18% respectively and enhanced accuracy.
Co-Authors Babu, Palepu Suresh Gopi, Pasala Karipireddy, Prasad Reddy Reddy, Manubolu Damodar Sarika, Daruru Venkata Sudhakar, Chowdam