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All Journal International Journal of Advanced Science Computing and Engineering
Azeez, Saba
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Computer Science & IT Control & Systems Engineering Electrical & Electronics Engineering

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FPGA Implementation of High Speed and Area Efficient Three Operand Binary Adder Azeez, Saba; Rangaree, Pankaj
International Journal of Advanced Science Computing and Engineering Vol. 3 No. 1 (2021)
Publisher : SOTVI

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (422.642 KB) | DOI: 10.62527/ijasce.3.1.34

Abstract

Three operand binary adder is the basic functional unit to perform the pseudorandom bit generator algorithms and in various cryptography. The basic method used to perform the three-operand binary addition is carry save adder, which leads to high delay. For this a parallel prefix two operand adder such as Han-Carlson adder is used to reduce the delay but increases the hardware architecture i.e., area increases. To overcome this disadvantage, we need a new area efficient and high-speed adder architecture to be proposed using pre compute bitwise addition followed by carry prefix computation logic to perform three operand binary adder which reduces delay and area efficiently. This method is the proposed method and implemented on the FPGA device. A newly designed three operand binary adder is shown and is implemented in MDCLCG. The results of 16 bit and 32-bit three operand adder will be shown and this proposed method is applied on Modified Dual CLCG. The Carry-Save-Adder architecture used in 32-bit MDCLCG is replaced by the proposed architecture. The design is prototyped on a commercially available FPGA platform to validate the design on silicon chip.
Co-Authors Rangaree, Pankaj