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All Journal IAES International Journal of Robotics and Automation (IJRA) International Journal of Informatics and Communication Technology (IJ-ICT)
Gorantla, Anusha
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Automotive Engineering Computer Science & IT Electrical & Electronics Engineering

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An improved approximate parallel prefix adder for high performance computing applications: a comparative analysis Anagani, Vamsidhar; Geethanjali, Kasi; Gorantla, Anusha; Devi, Annamreddy
International Journal of Informatics and Communication Technology (IJ-ICT) Vol 14, No 2: August 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijict.v14i2.pp382-392

Abstract

Binary adders are fundamental in digital circuit designs, including digital signal processors and microprocessor data path units. Consequently, significant research has focused on improving adders’ power-delay efficiency. The carry tree adder (CTA) is alternatively referred to as the parallel prefix adder (PPA), is among the fastest adders, achieving superior performance in very large scale integrated (VLSI) implementations through efficient concurrent carry generation and propagation. This study introduces approximate PPAs (AxPPAs) by applying approximations in prefix operators (POs). Four types of AxPPAs approximate kogge-stone, approximate brent-kung, approximate ladner fischer, and approximate sparse kogge-stone-were designed and implemented on FPGA with bit widths up to 64-bit. Delay measurements from static timing analysis using Xilinx ISE design suite version 14.7 indicate that AxPPAs exhibit better latency performance than traditional PPAs. The AxPPA sparse kogge-stone, in particular, demonstrated superior area and speed performance, achieving a delay of 2.501ns for a 16-bit addition.
Design of low-power, high-speed approximate 4:2 compressors for efficient partial product reduction in multipliers Michael, Jabez Daniel Vincent David; Gorantla, Anusha; Appathurai, Ahilan; Ramachandran, Dinesh
IAES International Journal of Robotics and Automation (IJRA) Vol 14, No 3: December 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijra.v14i3.pp459-467

Abstract

Partial product reduction becomes the main task in the multiplication process. Therefore, the partial product stages of multipliers are reduced with the usage of compressors, by using compressors in the multiplier. Using compressors in the multiplier circuit significantly impacts multiplier performance. Approximate compressors are crucial for achieving better design metrics in parallel multipliers. This paper proposes to create various new approximate 4:2 compressor circuits. A trade-off is made between the performance and accuracy of this approximate circuit design approach. The proposed designs have been implemented using XOR-XNOR gates with a 2-to-1 multiplexer, and also XOR-XNOR gates with transmission gates. All these circuits have been simulated using Cadence in different technological nodes. Compared with the existing technique, the proposed 4:2 approximation compressor provides 51.4% power reduction and 26.45% delay reduction for 45 nm equipment.
Co-Authors Anagani, Vamsidhar Appathurai, Ahilan Devi, Annamreddy Geethanjali, Kasi Michael, Jabez Daniel Vincent David Ramachandran, Dinesh