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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES) International Journal of Informatics and Communication Technology (IJ-ICT)
Reddy, Galiveeti Umamaheswara
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Computer Science & IT Economics, Econometrics & Finance

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Efficient design of approximate carry-based sum calculating full adders for error-tolerant applications Shiva Kumar, Badiganchela; Reddy, Galiveeti Umamaheswara
International Journal of Informatics and Communication Technology (IJ-ICT) Vol 14, No 3: December 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijict.v14i3.pp1189-1198

Abstract

Approximate computing is an innovative circuit design approach which can be applied in error-tolerant applications. This strategy introduces errors in computation to reduce an area and delay. The major power-consuming elements of full adder are XOR, AND, and OR operations. The sum computation in a conventional full adder is modified to produce an approximate sum which is calculated based on carry term. The major advantage of a proposed adder is the approximation error does not propagate to the next stages due to the error only in the sum term. The proposed adder was coded in verilog HDL and verified for different bit sizes. Results show that the proposed adder reduces hardware complexity with delay requirements.
Design and implementation of a novel approximate carry look ahead adder for low-power FIR filter applications Kumar, Badiganchela Shiva; Reddy, Galiveeti Umamaheswara
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 1: March 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i1.pp248-258

Abstract

Approximate computing is a low-power circuit design strategy that trades off computational accuracy for gains in speed, power efficiency, and area reduction. This approach achieves considerable power and area efficiency by introducing acceptable errors. The acceptable error in computation systems refers to a loss in accuracy that does not affect overall system performance. Approximate computing is mainly suitable for multimedia and signal processing applications. In this work, a novel approximate carry look-ahead adder (CLA) based on logical level modification is proposed. The new carry prediction term is derived to reduce the overall propagation delay of the addition operation. The proposed multi-bit adder design uses a square root based division method to partition the adder stages. Moreover, the proposed adder is applied in finite impulse response (FIR) filter implementation to evaluate the performance in real-time applications. The proposed adder and FIR filter are coded in Verilog and verified using the Xilinx simulator. The result shows that the proposed FIR filter achieves better results in terms of all parameters.
Co-Authors Kumar, Badiganchela Shiva Shiva Kumar, Badiganchela