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Sreenivasa, Kokila
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Optimizing timing closure and enhancing efficiency in RTL design: a focus on physical design tasks for I2C design blocks Ramegowda, Madhura; Hirebasur Krishnappa, Krutthika; Yamadur Venkatesh, Divyashree; Sreenivasa, Kokila
Indonesian Journal of Electrical Engineering and Computer Science Vol 39, No 3: September 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v39.i3.pp1525-1540

Abstract

Achieving precise timing closure in integrated circuit (IC) design is a significant challenge, especially with today's rapid technology advancements and intricate design specifications. Even with intense post-synthesis optimization, timing violations persist particularly in multi-corner, multi-mode designs. This research work emphasizes the necessity for power-efficient methods and streamlined approaches to boost timing closure and physical verification. Modern IC design thrives on effective physical design optimization strategies, usually tackled top-down. Clock tree synthesis (CTS) is transformative which effectively addresses clock deviation, latency, transition time, and insertion delay. This investigation mainly focuses on improving timing closure for inter integrated circuit (I2C) design blocks using custom-designed ccopt_spec and mmmc.tcl files to support multi-corner, multi-mode settings and significantly reduces register-to-register path violations from 80 to. 0. Additionally, the development and the usage of mmmc.tcl and global files are highlighted as critical components in the design process.
Co-Authors Hirebasur Krishnappa, Krutthika Ramegowda, Madhura Yamadur Venkatesh, Divyashree