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All Journal International Journal of Informatics and Communication Technology (IJ-ICT)
Thiagarajan, Sripriya
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Computer Science & IT

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A comparative study and design investigation: scalable magnitude comparators across technology nodes Juliette Albert, Anitha; Ramalingam, Umamaheswari; A. S., Ashlin Leon; Panneer Selvam, Sinthia; Thiagarajan, Sripriya; Kuppusamy, Arunkumar
International Journal of Informatics and Communication Technology (IJ-ICT) Vol 15, No 1: March 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijict.v15i1.pp13-20

Abstract

In recent times, the convergence of innovative design technologies such as very large-scale integration (VLSI), cadence design systems, and fieldprogrammable gate array (FPGA) has become crucial to address the growing demand for enhanced efficiency, scalability, and reduced power consumption in electronic designs. This paper introduces a novel approach to designing non-pipelined and pipelined scalable magnitude comparators (MCs), which integrates 4-bit MCs. The frontend implementation of the MCs is achieved using quartus prime, an FPGA board. The backend implementation is done using cadence design system, evaluated across the three distinct CMOS technology nodes. The literature review highlights the influence of technology scaling on area, power consumption, and propagation delay, analyzing various comparator designs and their associated trade-offs. The results provide valuable insights into the design and optimization of MCs for future applications in image processing and nano computing.
Co-Authors A. S., Ashlin Leon Juliette Albert, Anitha Kuppusamy, Arunkumar Panneer Selvam, Sinthia Ramalingam, Umamaheswari