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Giardino, Daniele
Department of Electronic Engineering, University of Rome Tor Vergata, Via Del Politecnico 1, Rome, 00133, Italy
Electrical & Electronics Engineering

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Efficient FPGA implementation of high speed digital delay for wideband beamforming using parallel architectures Carlo Cardarilli, Gian; Luca Di Nunzio, Ing.; Fazzolari, Rocco; Giardino, Daniele; Matta, Marco; Re, Marco; Spanò, Sergio; Simone, Lorenzo
Bulletin of Electrical Engineering and Informatics Vol 8, No 2: June 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/eei.v8i2.1483

Abstract

In this paper, the authors present an FPGA implementation of a digital delay for beamforming applications. The proposed digital delay is based on a new architecture about the Parallel FIR Filter which is used to describe the Parallel Farrow Filter. Such architecture allows to reach very high processing rate with wideband signals and it is suitable to be used along with Time-Interleaved Analog to Digital Converters (TI-ADC).
Co-Authors Gian Carlo Cardarilli, Gian Luca Di Nunzio, Ing. Marco Re, Marco Matta, Marco Rocco Fazzolari, Rocco Simone, Lorenzo Spanò, Sergio