Efficient FPGA implementation of high speed digital delay for wideband beamforming using parallel architectures

Gian Carlo Cardarilli (University of Rome Tor Vergata)
Luca Di Nunzio (University of Rome Tor Vergata)
Rocco Fazzolari (University of Rome Tor Vergata)
Daniele Giardino (University of Rome Tor Vergata)
Marco Matta (University of Rome Tor Vergata)
Marco Re (University of Rome Tor Vergata)
Sergio Spanò (University of Rome Tor Vergata)
Lorenzo Simone

Bulletin of Electrical Engineering and Informatics
Vol 8, No 2: June 2019

In this paper, the authors present an FPGA implementation of a digital delay for beamforming applications. The digital delay is based on a Parallel Farrow Filter. Such architecture allows to reach a very high processing rate with wideband signals and it is suitable to be used with Time-Interleaved Analog to Digital Converters (TI-ADC). The proposed delay has been simulated in MATLAB, implemented on FPGA and characterized in terms of amplitude and phase response, maximum clock frequency and area.