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All Journal TELKOMNIKA (Telecommunication Computing Electronics and Control) Bulletin of Electrical Engineering and Informatics Bulletin of Electrical Engineering and Informatics
Rocco Fazzolari
University of Rome Tor Vergata
Computer Science & IT Electrical & Electronics Engineering Engineering

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Approximated computing for low power neural networks Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Matta; Mario Patetta; Marco Re; Sergio Spanò
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 17, No 3: June 2019
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v17i3.12409

Abstract

This paper investigates about the possibility to reduce power consumption in Neural Network using approximated computing techniques. Authors compare a traditional fixed-point neuron with an approximated neuron composed of approximated multipliers and adder. Experiments show that in the proposed case of study (a wine classifier) the approximated neuron allows to save up to the 43% of the area, a power consumption saving of 35% and an improvement in the maximum clock frequency of 20%.
Energy Consumption Saving in Embedded Microprocessors Using Hardware Accelerators Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Marco Re; Francesca Silvestri; Sergio Spanò
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 16, No 3: June 2018
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v16i3.9387

Abstract

This paper deals with the reduction of power consumption in embedded microprocessors. Computing power and energy efficiency are becoming the main challenges for embedded system applications. This is, in particular, the caseof wearable systems. When the power supply is provided by batteries, an important requirement for these systems is the long service life. This work investigates a method for the reduction of microprocessor energy consumption, based on the use of hardware accelerators. Their use allows to reduce the execution time and to decrease the clock frequency, so reducing the power consumption. In order to provide experimental results, authors analyze a case of study in the field of wearable devices for the processing of ECG signals. The experimental results show that the use of hardware accelerator significantly reduces the power consumption.
Efficient FPGA implementation of high speed digital delay for wideband beamforming using parallel architectures Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Matta; Marco Re; Sergio Spanò; Lorenzo Simone
Bulletin of Electrical Engineering and Informatics Vol 8, No 2: June 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (903.688 KB) | DOI: 10.11591/eei.v8i2.1483

Abstract

In this paper, the authors present an FPGA implementation of a digital delay for beamforming applications. The digital delay is based on a Parallel Farrow Filter. Such architecture allows to reach a very high processing rate with wideband signals and it is suitable to be used with Time-Interleaved Analog to Digital Converters (TI-ADC). The proposed delay has been simulated in MATLAB, implemented on FPGA and characterized in terms of amplitude and phase response, maximum clock frequency and area.
Efficient FPGA implementation of high speed digital delay for wideband beamforming using parallel architectures Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Matta; Marco Re; Sergio Spanò; Lorenzo Simone
Bulletin of Electrical Engineering and Informatics Vol 8, No 2: June 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (903.688 KB) | DOI: 10.11591/eei.v8i2.1483

Abstract

In this paper, the authors present an FPGA implementation of a digital delay for beamforming applications. The digital delay is based on a Parallel Farrow Filter. Such architecture allows to reach a very high processing rate with wideband signals and it is suitable to be used with Time-Interleaved Analog to Digital Converters (TI-ADC). The proposed delay has been simulated in MATLAB, implemented on FPGA and characterized in terms of amplitude and phase response, maximum clock frequency and area.
Co-Authors Daniele Giardino Francesca Silvestri Gian Carlo Cardarilli Lorenzo Simone Luca Di Nunzio Marco Matta Marco Re Mario Patetta Sergio Spanò