<![CDATA[Synchronization is an essential process and one of the first tasks of the receiver in case of coherent communications as well synchronous digital data transfer. The phase lock loop (PLL), which employs the error tracking technique, has been a very popular way to implement this synchronizer since the early 1930s. A phenomenon called cycle slip occurs when the number of cycles present in the transmitted carrier (clock) differs from that of the recovered carrier (clock) at the receiver. The cycle slip can be very detrimental to some applications such as frequency modulated communications systems (FSK, multi-carrier etc.), burst digital data transfer, training pulse retrieval, and so on. This paper presents a remedy to avoid the cycle slip by using properly designed second-order Type II PLL.DOI:http://dx.doi.org/10.11591/ijece.v4i2.5048]]>
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