International Journal of Reconfigurable and Embedded Systems (IJRES)
Vol 6, No 3: November 2017

Online Self-testable Multi-core System using Dynamic Partial Reconfiguration of FPGA

G. Prasad Acharya (Sreenidhi Institute of Science and Technology)
M. Asha Rani (JNTU College of Engineering)



Article Info

Publish Date
28 May 2018

Abstract

This paper presents a novel and efficient method of designing an online self-testable multi-core system. Testing of a Core Under Test (CoUT) in a massively multi-core system can be carried out while the system is operational, by assigning the functionality of the CoUT to one of the non-functioning/idle and pre-tested core. The methodology presented in this paper has been implemented taking a test setup by demonstrating the Dynamic Partial Reconfiguration (DPR) feature of latest FPGAs on Zynq-7 XC702 evaluation board. The simulation results obtained from the experimental setup show that the utilization of a multi-core system can be significantly improved by effectively utilizing the idle core(s) to back up CoUT(s) for on-line test without a significant hardware overhead and test latency.

Copyrights © 2017






Journal Info

Abbrev

IJRES

Publisher

Subject

Economics, Econometrics & Finance

Description

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component ...