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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
G. Prasad Acharya
Sreenidhi Institute of Science and Technology
Economics, Econometrics & Finance

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Online Self-testable Multi-core System using Dynamic Partial Reconfiguration of FPGA G. Prasad Acharya; M. Asha Rani
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 3: November 2017
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (425.66 KB) | DOI: 10.11591/ijres.v6.i3.pp160-168

Abstract

This paper presents a novel and efficient method of designing an online self-testable multi-core system. Testing of a Core Under Test (CoUT) in a massively multi-core system can be carried out while the system is operational, by assigning the functionality of the CoUT to one of the non-functioning/idle and pre-tested core. The methodology presented in this paper has been implemented taking a test setup by demonstrating the Dynamic Partial Reconfiguration (DPR) feature of latest FPGAs on Zynq-7 XC702 evaluation board. The simulation results obtained from the experimental setup show that the utilization of a multi-core system can be significantly improved by effectively utilizing the idle core(s) to back up CoUT(s) for on-line test without a significant hardware overhead and test latency.
Berger Code Based Concurrent Online Self-Testing of Embedded Processors G. Prasad Acharya; M. Asha Rani
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 2: July 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (437.917 KB) | DOI: 10.11591/ijres.v7.i2.pp74-81

Abstract

In this paper, we propose an approach to detect the temporary faults induced by an environmental phenomenon called single event upset (SEU). Berger code based self-checking checkers provides an online detection of faults in digital circuits as well as in memory arrays. In this work, a concurrent Berger code based online self- testable methodology is proposed and integrated in 32-bit DLX Reduced Instruction Set Computer (RISC) processor on a single silicon chip. The proposed methodology is implemented and verified for various arithmetic and logical operations of the DLX processor. The FPGA implementation of the proposed design shows that a meager increase in hardware utilization facilitates online self- testing to detect temporary faults.
Co-Authors M. Asha Rani M. Asha Rani