International Journal of Reconfigurable and Embedded Systems (IJRES)
Vol 7, No 3: November 2018

Design And Analysis Of CMOS Low Noise Amplifier Circuit For 5-GHz Cascode and Folded Cascode In 180nm Technology

T. Kanthi (G.P.R.E.C)
D. Sharath Babu Rao (G.P.R.E.C)

Article Info

Publish Date
01 Nov 2018

Abstract

This paper is about Low noise amplifier topologies based on 0.18µm CMOS technology. A common source stage with inductive degeneration, cascode stage and folded cascode stage is designed, simulated and the performance has been analyzed. The LNA’s are designed in 5GHz. The LNA of cascode stage of noise figure (NF) 2.044dB and power gain 4.347 is achieved. The simulations are done in cadence virtuoso spectre RF.

Copyrights © 2018




Citation Download
RIS
EndNote, Reference Manager, ProCite
BibTex
Latex, Jabref
Full PDF
900.119 KB
Original Source
Download Original
Google Scholar
Check in Google Scholar
Journal Info
International Journal of Reconfigurable and Embedded Systems (IJRES)
Website

Abbrev

IJRES

Publisher

Institute of Advanced Engineering and Science

Subject

Economics, Econometrics & Finance

Description

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component ...