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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
T. Kanthi
G.P.R.E.C
Economics, Econometrics & Finance

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Design And Analysis Of CMOS Low Noise Amplifier Circuit For 5-GHz Cascode and Folded Cascode In 180nm Technology T. Kanthi; D. Sharath Babu Rao
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 3: November 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (900.119 KB) | DOI: 10.11591/ijres.v7.i3.pp149-156

Abstract

This paper is about Low noise amplifier topologies based on 0.18µm CMOS technology. A common source stage with inductive degeneration, cascode stage and folded cascode stage is designed, simulated and the performance has been analyzed. The LNA’s are designed in 5GHz. The LNA of cascode stage of noise figure (NF) 2.044dB and power gain 4.347 is achieved. The simulations are done in cadence virtuoso spectre RF.
Co-Authors D. Sharath Babu Rao