International Journal of Reconfigurable and Embedded Systems (IJRES)
Vol 2, No 1: March 2013

Configurable Router Design for Dynamically Reconfigurable Systems based on the SoCWire NoC

Arash Farhadi Beldachi (Bristol University)
Mohammad Hosseinabady (Queen'
s University Belfast)

Jose Luis Nunez-Yanez (Bristol University)



Article Info

Publish Date
01 Mar 2013

Abstract

New Field Programmable Gate Arrays (FPGAs) are capable of implementing complete multi-core System-on-Chip (SoC) with the possibility of modifying the hardware configuration at run-time with partial dynamic reconfiguration. The usage of a soft reconfigurable Network-on-Chip (NoC) to connect these cores is investigated in this paper. We have used a standard switch developed with the objective of supporting dynamically reconfigurable FPGAs as the starting point to create a novel configurable router. The configurable router uses distributed routing suitable for regular topologies and can vary the number of local ports and communication ports to build multi dimensional networks (i.e., 2D and 3D) with different topologies. The evaluation results show that the selection of the ideal router is different depending on traffic patterns and design objectives. Overall, the mesh network with a four local ports router offers a higher level of performance with lower complexity compared to the traditional mesh with one local port router.

Copyrights © 2013






Journal Info

Abbrev

IJRES

Publisher

Subject

Economics, Econometrics & Finance

Description

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component ...