FPGA-based architecture of hybrid multilayered perceptron neural network

Lee Yee Ann (Universiti Malaysia Perlis)
P. Ehkan (Universiti Malaysia Perlis)
M. Y. Mashor (Universiti Malaysia Perlis)
S. M. Sharun (Universiti Sultan Zainal Abidin)

Indonesian Journal of Electrical Engineering and Computer Science
Vol 14, No 2: May 2019

The HMLP is an ANN similar to the MLP, but with extra weighted connections that connect the input nodes directly to the output nodes. The architecture of the HMLP neural network for implementation on FPGA is proposed. The HMLP architecture is designed to be concurrent to demonstrate the parallel nature of the HMLP where each hidden or output node within the same hidden or output layer of the HMLP can calculate its output independently. The HMLP architecture is designed to be modular as well, such that if modification to a module is necessary, only the specific module need to be modified and all other modules can be retained. This modularity will be especially helpful when different activation function is to be swapped in to replace current activation function. All calculations in the HMLP are performed in floating-point arithmetic. The HMLP architecture is compiled, simulated and finally implemented on the Cyclone V FPGA of DE1-SoC board. The simulation outcome and FPGA outputs showed that the developed HMLP architecture is able to calculate correct output values for all test datasets.