A Comparative Studies of Cascaded Multilevel Inverters Having Reduced Number of Switches with R and RL-Load

Lipika Nanda (KIIT University)
Abhijit Dasgupta (KIIT University)
Ullash Kumar Rout

International Journal of Power Electronics and Drive Systems (IJPEDS)
Vol 8, No 1: March 2017

Multilevel inverter offers many benefits for high power application compavered to conventional cascaded Multilevel Inverter topology.This paper presents Symmetric CMLI using variable frequency carrier based pulse width modulation techniques. The proposed topology reduces total harmonic distortion and reduced switching losses for seven level inverter. The simulation study of the proposed topology has been carried out in MATLAB/SIMULINK. The main objective of this paper is to achieve number of levels of MLI with reduced number of switches and DC power sources compared to conventional topology.