JAREE (Journal on Advanced Research in Electrical Engineering)
Vol 1, No 1 (2017): April

Architecture of RAM-Accumulator based Multichannel Digital PWM

Norma Hermawan (Institut Teknologi Sepuluh Nopember)

Article Info

Publish Date
12 Jun 2017

Abstract

Traditional counter based digital Pulse Width Modulator (PWM) has been a straightforward architecture. However, realization of multichannel PWM with such design requires considerable logic gates. A novel architecture of multichannel PWM based on the usage of RAM block and frequency word accumulator is proposed. This architecture is capable of producing numerous channels while maintaining its performance. The design was tested in Microsemi SmartFusion A2F200 Customizable System on Chip, giving the result of 7.73% FPGA usage to produce 48 channels of 380Hz 16 bits PWM. The output performance for test application is acceptable. Keywords: PWM; RAM; accumulator; multichannel; digital

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Journal Info
JAREE (Journal on Advanced Research in Electrical Engineering)
Website

Abbrev

jaree

Publisher

Institut Teknologi Sepuluh Nopember Surabaya

Subject

Control & Systems Engineering Electrical & Electronics Engineering

Description

JAREE is an Open Access Journal published by the Department of Electrical Engineering, Institut Teknologi Sepuluh Nopember (ITS), Surabaya – Indonesia. Published twice a year every April and October, JAREE welcomes research papers with topics including power and energy systems, telecommunications ...