A power efficient delta-sigma ADC with series-bilinear switch capacitor voltage-controlled oscillator

D. S. Shylu (Karunya Institute of Technology & Sciences)
P. Sam Paul (Karunya Institute of Technology & Sciences)
D. Jackuline Moni (Karunya Institute of Technology & Sciences)
J. Arolin Monica Helan (Karunya Institute of Technology & Sciences)

TELKOMNIKA (Telecommunication Computing Electronics and Control)
Vol 18, No 5: October 2020

In low-power VLSI design applications non-linearity and harmonics are a major dominant factor which affects the performance of the ADC. To avoid this, the new architecture of voltage-controlled oscillator (VCO) was required to solve the non-linearity issues and harmonic distortion. In this work, a 12-bit, 200MS/s low power delta-sigma analog to digital converter (ADC) VCO based quantizer was designed using switched capacitor technique. The proposed technique uses frequency to current conversion technique as a linearization method to reduce the non-linearity issue. Simulation result show that the proposed 12-bit delta-sigma ADC consumes the power of 2.68 mW and a total area of 0.09 mm² in 90 nm CMOS process.