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D. S. Shylu
Karunya Institute of Technology & Sciences
Computer Science & IT

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A power efficient delta-sigma ADC with series-bilinear switch capacitor voltage-controlled oscillator D. S. Shylu; P. Sam Paul; D. Jackuline Moni; J. Arolin Monica Helan
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 18, No 5: October 2020
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v18i5.14034

Abstract

In low-power VLSI design applications non-linearity and harmonics are a major dominant factor which affects the performance of the ADC. To avoid this, the new architecture of voltage-controlled oscillator (VCO) was required to solve the non-linearity issues and harmonic distortion. In this work, a 12-bit, 200MS/s low power delta-sigma analog to digital converter (ADC) VCO based quantizer was designed using switched capacitor technique. The proposed technique uses frequency to current conversion technique as a linearization method to reduce the non-linearity issue. Simulation result show that the proposed 12-bit delta-sigma ADC consumes the power of 2.68 mW and a total area of 0.09 mm² in 90 nm CMOS process.
Co-Authors D. Jackuline Moni J. Arolin Monica Helan P. Sam Paul