Bulletin of Electrical Engineering and Informatics
Vol 10, No 6: December 2021

A review paper on memory fault models and test algorithms

Aiman Zakwan Jidin (Universiti Malaysia Perlis)
Razaidi Hussin (Universiti Malaysia Perlis)
Lee Weng Fook (Emerald Systems Sdn Bhd)
Mohd Syafiq Mispan (Universiti Teknikal Malaysia Melaka)



Article Info

Publish Date
01 Dec 2021

Abstract

Testing embedded memories in a chip can be very challenging due to their high-density nature and manufactured using very deep submicron (VDSM) technologies. In this review paper, functional fault models which may exist in the memory are described, in terms of their definition and detection requirement. Several memory testing algorithms that are used in memory built-in self-test (BIST) are discussed, in terms of test operation sequences, fault detection ability, and also test complexity. From the studies, it shows that tests with 22 N of complexity such as March SS and March AB are needed to detect all static unlinked or simple faults within the memory cells. The N in the algorithm complexity refers to Nx*Ny*Nz whereby Nx represents the number of rows, Ny represents the number of columns and Nz represents the number of banks. This paper also looks into optimization and further improvement that can be achieved on existing March test algorithms to increase the fault coverage or to reduce the test complexity.

Copyrights © 2021






Journal Info

Abbrev

EEI

Publisher

Subject

Electrical & Electronics Engineering

Description

Bulletin of Electrical Engineering and Informatics (Buletin Teknik Elektro dan Informatika) ISSN: 2089-3191, e-ISSN: 2302-9285 is open to submission from scholars and experts in the wide areas of electrical, electronics, instrumentation, control, telecommunication and computer engineering from the ...