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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES) Bulletin of Electrical Engineering and Informatics Indonesian Journal of Electrical Engineering and Computer Science
Razaidi Hussin
Universiti Malaysia Perlis
Economics, Econometrics & Finance Electrical & Electronics Engineering

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A review paper on memory fault models and test algorithms Aiman Zakwan Jidin; Razaidi Hussin; Lee Weng Fook; Mohd Syafiq Mispan
Bulletin of Electrical Engineering and Informatics Vol 10, No 6: December 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/eei.v10i6.3048

Abstract

Testing embedded memories in a chip can be very challenging due to their high-density nature and manufactured using very deep submicron (VDSM) technologies. In this review paper, functional fault models which may exist in the memory are described, in terms of their definition and detection requirement. Several memory testing algorithms that are used in memory built-in self-test (BIST) are discussed, in terms of test operation sequences, fault detection ability, and also test complexity. From the studies, it shows that tests with 22 N of complexity such as March SS and March AB are needed to detect all static unlinked or simple faults within the memory cells. The N in the algorithm complexity refers to Nx*Ny*Nz whereby Nx represents the number of rows, Ny represents the number of columns and Nz represents the number of banks. This paper also looks into optimization and further improvement that can be achieved on existing March test algorithms to increase the fault coverage or to reduce the test complexity.
Automatic generation of user-defined test algorithm description file for memory BIST implementation Aiman Zakwan Jidin; Razaidi Hussin; Lee Weng Fook; Mohd Syafiq Mispan; Loh Wan Ying
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 11, No 2: July 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v11.i2.pp103-114

Abstract

Memory built-in self-test (BIST) is a widely used technique to allow the self-test and self-checking of the embedded memories on chips after the fabrication process. It can be used by implementing a standard testing algorithm available in the EDA tool library or a user-defined algorithm (UDA). This paper presents the development of software that automatically generates a description file of a UDA to be deployed for memory BIST circuit implementation using Tessent memory BIST software. It comprises the test setup and also the microprogram coding for each instruction to be executed when performing tests on embedded memories. The proposed automation software was tested by using March SR as the input algorithm and the results obtained from the simulations show that the output test patterns generated by the implemented memory BIST match the expected patterns and passed all the tests, which validated the correct functionality of the UDA description file generation. The proposed automation software also fast generation the UDA description file, which was completed in less than 500 ms.
Less memory and high accuracy logarithmic number system architecture for arithmetic operations Siti Zarina Md Naziri; Rizalafande Che Ismail; Mohd Nazrin Md Isa; Razaidi Hussin
Indonesian Journal of Electrical Engineering and Computer Science Vol 23, No 3: September 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v23.i3.pp1708-1717

Abstract

Interpolation is another important procedure for logarithmic number system (LNS) addition and subtraction. As a medium of approximation, the interpolation procedure has an urgent need to be enhanced to increase the accuracy of the operation results. Previously, most of the interpolation procedures utilized the first degree interpolators with special error correction procedure which aim to eliminate additional embedded multiplications. However, the interpolation procedure for this research was elevated up to a second degree interpolation. Proper design process, investigation, and analysis were done for these interpolation configurations in positive region by standardizing the same co-transformation procedure, which is the extended range, second order co-transformation. Newton divided differences turned out to be the best interpolator for second degree implementation of LNS addition and subtraction, with the best-achieved BTFP rate of +0.4514 and reduction of memory consumption compared to the same arithmetic used in european logarithmic microprocessor (ELM) up to 51%.
A comprehensive review of memory BIST algorithms for SRAM static fault detection Aiman Zakwan Jidin; Razaidi Hussin; Mohd Syafiq Mispan; Lee Weng Fook; Loh Wan Ying
Indonesian Journal of Electrical Engineering and Computer Science Vol 43, No 2: August 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v43.i2.pp400-412

Abstract

Memory built-in self-test (MBIST) has become an essential design-for testability technique for ensuring the reliability and quality of embedded memories in modern integrated circuits. The effectiveness of an MBIST implementation is largely determined by its test algorithm, which defines the sequence of memory operations, directly influencing both test complexity and fault coverage. Designing an efficient test algorithm requires balancing low test complexity with comprehensive fault detection. This paper presents a comprehensive review of MBIST test algorithms for static fault detection in static random-access memory (SRAM). The review first summarizes the characteristics of major SRAM static faults and their corresponding detection requirements. It then compares representative test algorithms in terms of test sequence, computational complexity, fault coverage, and design methodology. Furthermore, the evolution of MBIST test algorithm development is discussed, ranging from conventional ad hoc approaches to enhanced algorithms derived from existing March tests. The comparative analysis indicates that an 18N-complexity test algorithm is generally required to achieve complete detection of all unlinked static faults in SRAM, whereas optimized 14N-complexity algorithms provide an effective trade-off between test time and fault coverage. Finally, the review identifies current research challenges, including efficient detection of dynamic and linked memory faults and the development of MBIST algorithms for emerging memory technologies such as magnetic random-access memory (MRAM), highlighting promising directions for future research.
Co-Authors Aiman Zakwan Jidin Aiman Zakwan Jidin Aiman Zakwan Jidin Lee Weng Fook Lee Weng Fook Lee Weng Fook Loh Wan Ying Mohd Nazrin Md Isa Mohd Syafiq Mispan Rizalafande Che Ismail Siti Zarina Md Naziri