<![CDATA[Growing endless demand for digital processing technology, to perform high speed computations with low power utilization and minimum propagation delay, the metal-oxide-semiconductor (MOS) technology is implemented in the areas of very large scale integrated (VLSI) circuit technology. But MOS technology is facing the challenges in linear scaling the transistors with different channel modelling for the present day microelectronic regime. Linear scaling of MOSFET is restricted through short-channel-effects (SCEs). Use of silicon N-channel double gate MOSFETs (DG MOSFETs) in present day microelectronic regime features the short channel effect of MOSFET through a reasaonable forward transfer admittance with the characteristics of varying input capacitance values ratio. In this research paper, a distinct ρ-based model is designed to simulate SCEs through the designed silicon N-channel double gate MOSFETs with the varying front and back gate doping level and surface regions to estimate the varying junction capacitances can limit the intrusion detection systems (IDS) usage in VLSI applications. Analytical model for channel length and simulated model for total internal device capacitance through distinct ρ-based model are presented. The proposed distinct ρ-based model is suitable for silicon nanowire transistors and the effectiveness of the proposed model is validated through comparative results.]]>
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