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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES) Indonesian Journal of Electrical Engineering and Computer Science
Udara Yedukondalu
Sri Vasavi Engineering College
Economics, Econometrics & Finance

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Distinct ρ-based model of silicon N-channel double gate MOSFET Hameed Pasha Mohammad; H. C. Hadimani; Udara Yedukondalu; Srinivasa Rao Udara
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 11, No 1: March 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v11.i1.pp71-83

Abstract

Growing endless demand for digital processing technology, to perform high speed computations with low power utilization and minimum propagation delay, the metal-oxide-semiconductor (MOS) technology is implemented in the areas of very large scale integrated (VLSI) circuit technology. But MOS technology is facing the challenges in linear scaling the transistors with different channel modelling for the present day microelectronic regime. Linear scaling of MOSFET is restricted through short-channel-effects (SCEs). Use of silicon N-channel double gate MOSFETs (DG MOSFETs) in present day microelectronic regime features the short channel effect of MOSFET through a reasaonable forward transfer admittance with the characteristics of varying input capacitance values ratio. In this research paper, a distinct ρ-based model is designed to simulate SCEs through the designed silicon N-channel double gate MOSFETs with the varying front and back gate doping level and surface regions to estimate the varying junction capacitances can limit the intrusion detection systems (IDS) usage in VLSI applications. Analytical model for channel length and simulated model for total internal device capacitance through distinct ρ-based model are presented. The proposed distinct ρ-based model is suitable for silicon nanowire transistors and the effectiveness of the proposed model is validated through comparative results.
Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application Udara Yedukondalu; Vinod Arunachalam; Vasudha Vijayasri Bolisetty; Ravikumar Guru Samy
Indonesian Journal of Electrical Engineering and Computer Science Vol 28, No 2: November 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v28.i2.pp716-723

Abstract

The paper presents the implementation of a standard cell multigate fully synthesizable rail-to-rail dynamic voltage comparator. The dynamic voltage comparator works on deep sub-threshold supply voltage VDD =0.3 V with common mode inputs. The common-mode input range is VDD/2 with minimum input offset voltage ranging between 8mV to 28mV. Thus the circuit is simulated at 180nm Complementary Metal-Oxide Semiconductor (CMOS) process. Hence the dynamic voltage comparator has measured and tabulated by corresponding output voltage, power dissipation. But the performance of CMOS device is not good when compared with Fin Field-Effect Transistor (FinFET) device. The leakage current is more in CMOS devices while in FinFET device due to the control of multi-Gates on the channel, the leakage current is reduced. This will improve the power consumption in the FinFET device when compared to CMOS devices. The comparator results shows that CMOS device is inferior when compared with FinFET device comparator. For the implementation of the comparator Spice model were used in this work. The software used in the project is synopsis Hspice.
Co-Authors H. C. Hadimani Hameed Pasha Mohammad Ravikumar Guru Samy Srinivasa Rao Udara Vasudha Vijayasri Bolisetty Vinod Arunachalam