Delay-power efficient VLSI architecture design for robust proportionate adaptive filter

Gangadharaiah Soralamavu Lakshmaiah (M. S. Ramaiah Institute of Technology)
Chikkajala Krishnappa Narayanappa (M. S. Ramaiah Institute of Technology)
Divya Muddenahalli Narasimhaiah (M.S. Ramaiah Institute of Technology)
Munivenkatappa Nagabhushanam (M.S. Ramaiah Institute of Technology)
Nuthan Prasad Venkatesh (M.S. Ramaiah Institute of Technology)
Bhanu Darshan Srinivas Shobhavathi (M.S. Ramaiah Institute of Technology)

Indonesian Journal of Electrical Engineering and Computer Science
Vol 26, No 1: April 2022

This paper proposes the robust proportionate adaptive filtering algorithms and their respective efficient very large-scale integration (VLSI) architectures for sparse system identification under impulsive noise, several types of algorithms are combined to obtain optimum results. Here, we rendered a relative analysis on these algorithms and the algorithms are mapped on to the hardware to show that the improvement is obtained with respect to convergence rate and hardware complexity of VLSI architectures and has negligible hardware overhead with improved robustness. Good performance and convergence rate is obtained by combining the delayed μ-law proportionate (DMP) and least mean logarithmic square (LMLS) algorithms i.e. delayed µ-law proportionate least mean logarithmic square (DMP LMLS). Robust proportionate adaptive filter is coded in system verilog and synthesized using cadence genus compiler with 90 nm technology library.