International Journal of Reconfigurable and Embedded Systems (IJRES)
Vol 12, No 1: March 2023

Side channel power analysis resistance evaluation of masked adders on FPGA

Yilin Zhao (Ritsumeikan University)
Hiroki Nishikawa (Osaka University)
Xiangbo Kong (Ritsumeikan University)
Hiroyuki Tomiyama (Ritsumeikan University)



Article Info

Publish Date
01 Mar 2023

Abstract

Since many internet of things (IoT) devices are threatened by side-channel attacks, security measures are essential for their safe use. However, there are a variety of IoT devices, so the accuracy required depends on the system’s application. In addition, security related to arithmetic operations has been attracting attention in recent years. Therefore, this paper presents an empirical experiment of masking for adders on field programmable gate arrays (FPGAs) and explores the trade-off between cost and security by varying the bit length of the mask. The experimental results show that masking improves power analysis attack resistance, and increasing the bit length of the random numbers used for masking increases security. In particular, the series-connected masked adder is found to be effective in improving power analysis attack resistance.

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Journal Info

Abbrev

IJRES

Publisher

Subject

Economics, Econometrics & Finance

Description

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component ...