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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Hiroyuki Tomiyama
Ritsumeikan University
Economics, Econometrics & Finance

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Heuristic algorithms for dynamic scheduling of moldable tasks in multicore embedded systems Takuma Hikida; Hiroki Nishikawa; Hiroyuki Tomiyama
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 3: November 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v10.i3.pp157-167

Abstract

Dynamic scheduling of parallel tasks is one of the efficient techniques to achieve high performance in multicore systems. Most existing algorithms for dynamic task scheduling assume that a task runs on one of the multiple cores or a fixed number of cores. Existing researches on dynamic task scheduling methods have evaluated their methods in different experimental environments and models. In this paper, the dynamic task scheduling methods are systematically rearranged and evaluated.
A design methodology for approximate multipliers in convolutional neural networks: A case of MNIST Kenta Shirane; Takahiro Yamamoto; Hiroyuki Tomiyama
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 1: March 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v10.i1.pp1-10

Abstract

In this paper, we present a case study on approximate multipliers for MNIST Convolutional Neural Network (CNN). We apply approximate multipliers with different bit-width to the convolution layer in MNIST CNN, evaluate the accuracy of MNIST classification, and analyze the trade-off between approximate multiplier’s area, critical path delay and the accuracy. Based on the results of the evaluation and analysis, we propose a design methodology for approximate multipliers. The approximate multipliers consist of some partial products, which are carefully selected according to the CNN input. With this methodology, we further reduce the area and the delay of the multipliers with keeping high accuracy of the MNIST classification.
Side channel power analysis resistance evaluation of masked adders on FPGA Yilin Zhao; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 1: March 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i1.pp97-112

Abstract

Since many internet of things (IoT) devices are threatened by side-channel attacks, security measures are essential for their safe use. However, there are a variety of IoT devices, so the accuracy required depends on the system’s application. In addition, security related to arithmetic operations has been attracting attention in recent years. Therefore, this paper presents an empirical experiment of masking for adders on field programmable gate arrays (FPGAs) and explores the trade-off between cost and security by varying the bit length of the mask. The experimental results show that masking improves power analysis attack resistance, and increasing the bit length of the random numbers used for masking increases security. In particular, the series-connected masked adder is found to be effective in improving power analysis attack resistance.
Empirical analysis of power side-channel leakage of high-level synthesis designed AES circuits Takumi Mizuno; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 3: November 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i3.pp305-319

Abstract

Many internet of things (IoT) devices and integrated circuit (IC) cards have been compromised by side-channel attacks. Power-analysis attacks, which identify the secret key of a cryptographic circuit by analyzing the power traces, are among the most dangerous side-channel attacks. Gen-erally, there is a trade-off between execution time and circuit area. However, the correlation between security and performance has yet to be determined. In this study, we investigate the cor-relation between side-channel attack resistance and performance (execution time and circuit area) of advanced encryption standard (AES) circuits. Eleven AES circuits with different performances are designed by high-level synthesis and logic synthesis. Of the eleven AES circuits, six are circuits with no side-channel attack countermeasures and five are circuits with masking countermeasures. We employ four metrics based on a T-test to evaluate the side-channel attack resistance. The results based on the correlation coefficient show the correlation between side-channel attack resistance and performance. The correlation varies according to four metrics or masking countermeasure. We argue that designers should change their attitudes towards circuit design when considering security.
Co-Authors Hiroki Nishikawa Hiroki Nishikawa Kenta Shirane Takahiro Yamamoto Takuma Hikida Takumi Mizuno Xiangbo Kong Yilin Zhao