Reduced switched seven level multilevel inverter by modified carrier for high voltage industrial applications

Sanka Sreelakshmi (Jawaharlal Nehru Technological University)
Machineni Sanjeevappa Sujatha (Sree Vidyanikethan Engineering College)
Jammy Ramesh Rahul (Gayatri Vidya Parishad College of Engineering (A))
Tole Sutikno (Universitas Ahmad Dahlan)

International Journal of Power Electronics and Drive Systems (IJPEDS)
Vol 14, No 2: June 2023

Multilevel inverters are widely used in high-power and high-voltage applications due to their lower total harmonic distortion (THD), decreased switching stress on their switches, and other benefits. However, increasing the number of steps results in a drop in THD, which results in a larger size. As a result, a new 7-level reduced switched cascaded multilevel inverter (CMLI) has been designed for the current project. This architecture employs seven switches and seven levels of MLI to achieve the same output as a conservative multilevel inverter (MLI). To generate gate pulses for the switches, conventional and modified carriers were employed, and a third harmonic component was added into the sine wave to increase the fundamental output voltage. Finally, MATLAB or simulation is utilized to test the results of this task's design. According to the analysis, the proposed design may reduce harmonic distortion and improve the fundamental voltage component with fewer switches.