<![CDATA[This paper focuses on designing a 32-bit Reduced Instruction Set Computer (RISC) Scalable Processor Architecture (SPArc) subset gener al purposes processor. The design process covers instructions selection, Register Transfer Notation (RTN) design, Datapath Design, and Control Unit Design. Basic integer instruction was selected. Datapath was designed along with the RTN with a five-stage pipeline with direct connection between stages. This design was then validated using functionality simulation test and implemented in Field Programmable Gate Array (FPGA). The performance of the processor was measured using thermal report, power report, and time report. Functional test shows that the Processor can execute instructions as designed, which are Arithmetic/Shift/Logic, Control Transfers, and Memory access instructions. It was validated with the register content and signal generated in each stage. The design was also successfully implemented in FPGA with the maximum clock of 58 MHz as the synthesis report shows. Thermal report shows the thermal properties of the design, which shown the acceptable thermal margin of 56.9 ?C and junction temperature of 28.1 ?C. The power report shows the low power consumption of 0.266 W, which consists of dynamic power of 0.173 W and static power of 0.093 W. This work enables further development and to be used as master processor in System on Chip design of special purpose processors like cognitive processors]]>
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