<![CDATA[The Discrete Cosine Transform (DCT) is the most commonly used transformation technique in image processing applications for data compression. It transforms a finite set of data points or pixels into frequency domain in terms of sum of cosine coefficients of various frequencies. This paper proposes an optimized hardware architecture for 2D 8x8 Discrete and Inverse discrete cosine transforms (DCT and IDCT) using Loeffler’s algorithm. The hardware architecture is optimized using efficient adders and multipliers. Modified carry select adders (CSLA) are used to boost the speed, wherein Booth multipliers improve overall performance of the design. The Loeffler’s algorithm consisting of 8-stage pipelined architecture reduces the arithmetic operations per cycle and improves processor efficiency. The front-end RTL design of the proposed architecture is implemented on Virtex-7 FPGA, while the backend design is implemented in Cadence using 45nm CMOS technology. The proposed design possesses 24% lesser area, 25% lesser leakage power and 8.8% lesser delay than the existing designs.]]>
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