Optimizing the implementation of the Saber post-quantum cryptography scheme with a hybrid architecture

Sabyrzhan Atanov (L.N. Gumilyov Eurasian National University)
Khuralay Moldamurat (L.N. Gumilyov Eurasian National University)
Luigi La Spada (Edinburgh Napier University)
Makhabbat Bakyt (L.N. Gumilyov Eurasian National University)
Adil Maidanov (L.N. Gumilyov Eurasian National University)

Bulletin of Electrical Engineering and Informatics
Vol 15, No 1: February 2026

This paper presents a hardware–software hybrid implementation of the Saber key encapsulation mechanism (KEM) on a Terasic DE10-Nano board, which combines an ARM Cortex-A9 processor and an Intel Cyclone V field programmable gate array (FPGA). By offloading computationally intensive polynomial multiplication to a dedicated FPGA module, the hybrid design significantly reduces execution time. Experimental results show that compared to a software-only approach, the hybrid design decreases execution time by 40% for key generation, 35% for encapsulation, and 50% for decapsulation. The consistent performance gains were confirmed across the LightSaber, Saber, and FireSaber parameter sets, demonstrating that CPU-FPGA co-design offers significant efficiency improvements for post quantum cryptography (PQC), especially on platforms with limited resources.