Bulletin of Electrical Engineering and Informatics
Vol 15, No 5: October 2026

Finite-set MPC for a 7-level cascaded H-bridge simulation-based evaluation with reference extrapolation and non-idealities

Asep Andang (Universitas Siliwangi)
Muhammad Aris Risnandar (Universitas Siliwangi)
Imam Taufiqurrahman (Universitas Siliwangi)
Rizal Anshor (Universitas Siliwangi)
Miftahul Huda Pratama (Universitas Siliwangi)
Muhammad Lutfi Azhari (Universitas Siliwangi)



Article Info

Publish Date
01 Oct 2026

Abstract

Multilevel cascaded H-bridge (CHB) inverters are widely used in power conversion systems because they can create high-quality voltage waveforms with low harmonic distortion. However, the predictive control of multilevel converters faces challenges such as computational delays, switching dynamics, and maintaining performance under nonideal conditions. This study explores finite-control-set model predictive control for a three-phase seven-level CHB inverter with an inductor capacitor inductor (LCL) filter, taking into account hardware-related imperfections. A discrete state-space model and a voltage-tracking cost function are used to assess 343 possible switching vectors at each sampling interval. Second-order reference extrapolation is applied to manage the typical one-sample actuation delay in real-time digital systems. Simulation results show that, in ideal conditions, the inverter achieves a voltage total harmonic distortion (THD) of less than 0.1% and a power factor close to one. Under realistic disturbances, such as dc-link voltage drops and load imbalances, the system remained stable, with the THD increasing slightly to approximately 5%. Thus, the controller maintains good waveform quality and dynamic stability despite common disturbances in converter operations and digital control limits. The main contribution is integrating second-order reference extrapolation within a hardware-aware finite-control-set model predictive control (FCS-MPC) framework, providing a practical basis for future real-time implementation and validation through processor-in-the-loop (PIL) or hardware-in-the-loop testing.

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Journal Info

Abbrev

EEI

Publisher

Subject

Electrical & Electronics Engineering

Description

Bulletin of Electrical Engineering and Informatics (Buletin Teknik Elektro dan Informatika) ISSN: 2089-3191, e-ISSN: 2302-9285 is open to submission from scholars and experts in the wide areas of electrical, electronics, instrumentation, control, telecommunication and computer engineering from the ...