DESIGN AND IMPLEMENTATION OF A VHDL PROCESSOR FOR DCT BASED IMAGE COMPRESSION

Md. Shabiul Islam (Faculty of Engineering, Multimedia University, 63100 Cyberjaya)
M.S. Bhuyan (Faculty of Engineering, Multimedia University, 63100 Cyberjaya)
M. Salim Beg (Dept. of Engineering, Aligarh University, Aligarh 202 002 (U.P))
Masuri Othman (Dept. of Electrical Engineering, University Kebangsaan Malaysia, Bangi)

ASEAN Journal on Science and Technology for Development
Vol. 24 No. 4 (2007): ASEAN Journal on Science and Technology for Development (AJSTD)

This paper describes the design and implementation of a VHDL processor meant for performing 2D-Discrete Cosine Transform (DCT) to use in image compression applications. The design flow starts from the system specification to implementation on silicon and the entire process is carried out using an advanced workstation based design environment for digital signal processing. The software allows the bit-true analysis to ensure that the designed VLSI processor satisfies the required specifications. The bit-true analysis is performed on all levels of abstraction (behavior, VHDL etc.). The motivation behind the work is smaller size chip area, faster processing, reducing the cost of the chip