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International Journal of Electrical and Computer Engineering
ISSN : 20888708     EISSN : 27222578     DOI : -
International Journal of Electrical and Computer Engineering (IJECE, ISSN: 2088-8708, a SCOPUS indexed Journal, SNIP: 1.001; SJR: 0.296; CiteScore: 0.99; SJR & CiteScore Q2 on both of the Electrical & Electronics Engineering, and Computer Science) is the official publication of the Institute of Advanced Engineering and Science (IAES). The journal is open to submission from scholars and experts in the wide areas of electrical, electronics, instrumentation, control, telecommunication and computer engineering from the global world.
Articles 96 Documents
Search results for , issue "Vol 11, No 3: June 2021" : 96 Documents clear
Enhancing three variants of harmony search algorithm for continuous optimization problems Alaa A. Alomoush; Abdul Rahman A. Alsewari; Kamal Z. Zamli; Ayat Alrosan; Waleed Alomoush; Khalid Alissa
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 3: June 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v11i3.pp2343-2349

Abstract

Meta-heuristic algorithms are well-known optimization methods, for solving real-world optimization problems. Harmony search (HS) is a recognized meta-heuristic algorithm with an efficient exploration process. But the HS has a slow convergence rate, which causes the algorithm to have a weak exploitation process in finding the global optima. Different variants of HS introduced in the literature to enhance the algorithm and fix its problems, but in most cases, the algorithm still has a slow convergence rate. Meanwhile, opposition-based learning (OBL), is an effective technique used to improve the performance of different optimization algorithms, including HS. In this work, we adopted a new improved version of OBL, to improve three variants of Harmony Search, by increasing the convergence rate speed of these variants and improving overall performance. The new OBL version named improved opposition-based learning (IOBL), and it is different from the original OBL by adopting randomness to increase the solution's diversity. To evaluate the hybrid algorithms, we run it on benchmark functions to compare the obtained results with its original versions. The obtained results show that the new hybrid algorithms more efficient compared to the original versions of HS. A convergence rate graph is also used to show the overall performance of the new algorithms.
Fog computing scheduling algorithm for smart city Ahmad Mohammad Alsmadi; Roba Mahmoud Ali Aloglah; Nisrein Jamal sanad Abu-darwish; Ahmad Al Smadi; Muneerah Alshabanah; Daniah Alrajhi; Hanouf Alkhaldi; Mutasem K. Alsmadi
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 3: June 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v11i3.pp2219-2228

Abstract

With the advent of the number of smart devices across the globe, increasing the number of users using the Internet. The main aim of the fog computing (FC) paradigm is to connect huge number of smart objects (billions of object) that can make a bright future for smart cities. Due to the large deployments of smart devices, devices are expected to generate huge amounts of data and forward the data through the Internet. FC also refers to an edge computing framework that mitigates the issue by applying the process of knowledge discovery using a data analysis approach to the edges. Thus, the FC approaches can work together with the internet of things (IoT) world, which can build a sustainable infrastructure for smart cities. In this paper, we propose a scheduling algorithm namely the weighted round-robin (WRR) scheduling algorithm to execute the task from one fog node (FN) to another fog node to the cloud. Firstly, a fog simulator is used with the emergent concept of FC to design IoT infrastructure for smart cities. Then, spanning-tree routing (STP) protocol is used for data collection and routing. Further, 5G networks are proposed to establish fast transmission and communication between users. Finally, the performance of our proposed system is evaluated in terms of response time, latency, and amount of data used.
Reducing power consumption in LEO satellite network Mohammed Hussein; Abdellatif Abu-Issa; Iyad Tumar; Abdalkarim Awad
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 3: June 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v11i3.pp2256-2265

Abstract

Current low earth orbit (LEO) satellite network display poor power efficiency, running network devices at full capacity all the time regardless of the traffic matrix and the distribution of the population over the Globe. Most of the research on energy efficiency of LEO satellites has focused on component level or link level. Therefore, this kind of research is not holistic to try to look at the satellite system as a single node. To enhance the energy efficiency. The solution should exploits multipath routing and load balancing. LEO network is overprovisioned, and hence selectively shutting down some satellite nodes and links during off-peaks hours seems like a good way to reduce energy consumption. In this paper, we exploit the fact that due to geographical and climatic conditions, some satellite links are expected to be loaded with data while others remain unused. Our approach is to power down satellite nodes and links during period of low traffic, while guaranteeing the connectivity and QoS. Finding the optimal solution is NP-problem and therefore, we explore in this work two heuristic algorithms. We evaluate our heuristics on a realistic LEO topology and real traffic matrices. Simulation results show that the power saving can be significant.
ANFIS control of a shunt active filter based with a five-level NPC inverter to improve power quality Mahmoud Mostefa Tounsi; Ahmed Allali; Houari Merabet Boulouiha; Mouloud Denaï
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 3: June 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v11i3.pp1886-1893

Abstract

This paper addresses the problem of power quality, and the degradation of the current waveform in the distribution network which results directly from the proliferation of the nonlinear loads. We propose to use a five-level neutral point clamped (NPC) inverter topology for the implementation of the shunt active filter (SAPF). The aim of the SAPF is to inject harmonic currents in phase opposition at the connection point. The identification of harmonics is based on the pq method. A neuro-fuzzy controller based on ANFIS (adaptive neuro fuzzy inference system) is designed for the SAPF. The simulation study is carried out using MATLAB/Simulink and the results show a significant improvement in the quality of energy and a reduction in total harmonic distortion (THD) in accordance with IEC standard, IEEE-519, IEC 61000, EN 50160.
High clarity speech separation using synchro extracting transform Shahin M. Abdulla; J. Jayakumari
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 3: June 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v11i3.pp2621-2630

Abstract

Degenerate unmixing estimation technique (DUET) is the most ideal blind source separation (BSS) method for underdetermined conditions with number of sources exceeds number of mixtures. Estimation of mixing parameters which is the most critical step in the DUET algorithm, is developed based on the characteristic feature of sparseness of speech signals in time frequency (TF) domain. Hence, DUET relies on the clarity of time frequency representation (TFR) and even the slightest interference in the TF plane will be detrimental to the unmixing performance. In conventional DUET algorithm, short time Fourier transform (STFT) is utilized for extracting the TFR of speech signals. However, STFT can provide on limited sharpness to the TFR due to its inherent conceptual limitations, which worsens under noise contamination. This paper presents the application of post-processing techniques like synchro squeezed transform (SST) and synchro extracting transform (SET) to the DUET algorithm, to improve the TF resolution. The performance enhancement is evaluated both qualitatively and quantitatively by visual inspection, Renyi entropy of TFR and objective measures of speech signals. The results show enhancement in TF resolution and high clarity signal reconstruction. The method also provides adequate robustness to noise contamination.
Outage performance of underlay cognitive radio networks over mix fading environment Nguyen Hong Nhu; Cuu Ho Van; Van-Duc Phan; Tan N. Nguyen; Miroslav Voznak; Jaroslav Zdralek
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 3: June 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v11i3.pp2019-2026

Abstract

In this paper, the underlay cognitive radio network over mix fading environment is presented and investigated. A cooperative cognitive system with a secondary source node S, a secondary destination node D, secondary relay node Relay, and a primary node P are considered. In this model system, we consider the mix fading environment in two scenarios as Rayleigh/Nakagami-m and Nakagami-m/Rayleigh Fading channels. For system performance analysis, the closed-form expression of the system outage probability (OP) and the integral-formed expression of the ergodic capacity (EC) are derived in connection with the system's primary parameters. Finally, we proposed the Monte Carlo simulation for convincing the correctness of the system performance.
Chirplet signal design by FPGA Mohammed Jawad Al-Dujaili; Aws Majeed Al-Awadi
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 3: June 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v11i3.pp2120-2127

Abstract

The ever-expanding growth of the electronics and communications industries present new challenges for researchers. One of these challenges is the generation of the required bandwidth signal over a specific time frame that is used in a variety of contexts, particularly radar systems. To improve the range resolution in the radar along with better SNR, it is necessary to reduce the signal bandwidth and increase the peak power. There are some restrictions for narrowband signals like power limitation, pulse shaping, and the production of unwanted harmonics. So as a solution pulse compression techniques are suggested. Pulse compression is a process that modulating the transmitted pulse to achieve a wideband signal and then at the receiver, the received signal correlates with the transmitted pulse to achieve narrowband representations of data. Chirp is the most common signal used in pulse compression. The chirp signal is produced using linear frequency modulation. In this study, we attempted to add an amplitude modulation to the chirp signal and evaluate its performance by implementation on FPGA. The outcome signal is called chirplet and simulation will show that it enhance target detection and image quality in imaging radars like SAR.
Visual victim detection and quadrotor-swarm coordination control in search and rescue environment Gustavo A. Cardona; Juan Ramirez-Rugeles; Eduardo Mojica-Nava; Juan M. Calderon
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 3: June 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v11i3.pp2079-2089

Abstract

We propose a distributed victim-detection algorithm through visual information on quadrotors using convolutional neuronal networks (CNN) in a search and rescue environment. Describing the navigation algorithm, which allows quadrotors to avoid collisions. Secondly, when one quadrotor detects a possible victim, it causes its closest neighbors to disconnect from the main swarm and form a new sub-swarm around the victim, which validates the victim’s status. Thus, a formation control that permits to acquire information is performed based on the well-known rendezvous consensus algorithm. Finally, images are processed using CNN identifying potential victims in the area. Given the uncertainty of the victim detection measurement among quadrotors’ cameras in the image processing, estimation consensus (EC) and max-estimation consensus (M-EC) algorithms are proposed focusing on agreeing over the victim detection estimation. We illustrate that M-EC delivers better results than EC in scenarios with poor visibility and uncertainty produced by fire and smoke. The algorithm proves that distributed fashion can obtain a more accurate result in decision-making on whether or not there is a victim, showing robustness under uncertainties and wrong measurements in comparison when a single quadrotor performs the mission. The well-functioning of the algorithm is evaluated by carrying out a simulation using V-Rep.
History-based consistency algorithm for the trickle-timer with low-power and lossy networks Firas A. Albalas; Haneen Taamneh; Wail E. Mardini
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 3: June 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v11i3.pp2569-2576

Abstract

Recently, the internet of things (IoT) has become an important concept which has changed the vision of the Internet with the appearance of IPv6 over low power and lossy networks (6LoWPAN). However, these 6LoWPANs have many drawbacks because of the use of many devices with limited resources; therefore, suitable protocols such as the Routing Protocol for low power and lossy networks (RPL) were developed, and one of RPL's main components is the trickle timer algorithm, used to control and maintain the routing traffic frequency caused by a set of control messages. However, the trickle timer suffered from the short-listen problem which was handled by adding the listen-only period mechanism. This addition increased the delay in propagating transmissions and resolving the inconsistency in the network. However, to solve this problem we proposed the history based consistency algorithm (HBC), which eliminates the listen-only period based on the consistency period of the network. The proposed algorithm showed very good results. We measured the performance of HBC trickle in terms of convergence time; which was mainly affected, the power consumption and the packet delivery ratio (PDR). We made a comparison between the original trickle timer, the E-Trickle, the optimized trickle and our HBC trickle algorithm. The PDR and the power consumption showed in some cases better results under the HBC trickle compared to other trickle timers and in other cases the results were very close to the original trickle indicating the efficiency of the proposed trickle in choosing optimal routes when sending messages.
TFI-FTS: An efficient transient fault injection and fault-tolerant system for asynchronous circuits on FPGA platform Sharath Kumar Y. N.; Dinesha P.
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 3: June 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v11i3.pp2704-2710

Abstract

Designing VLSI digital circuits is challenging tasks because of testing the circuits concerning design time. The reliability and productivity of digital integrated circuits are primarily affected by the defects in the manufacturing process or systems. If the defects are more in the systems, which leads the fault in the systems. The fault tolerant systems are necessary to overcome the faults in the VLSI digital circuits. In this research article, an asynchronous circuits based an effective transient fault injection (TFI) and fault tolerant system (FTS) are modelled. The TFI system generates the faults based on BMA based LFSR with faulty logic insertion and one hot encoded register. The BMA based LFSR reduces the hardware complexity with less power consumption on-chip than standard LFSR method. The FTS uses triple mode redundancy (TMR) based majority voter logic (MVL) to tolerant the faults for asynchronous circuits. The benchmarked 74X-series circuits are considered as an asynchronous circuit for TMR logic. The TFI-FTS module is modeled using Verilog-HDL on Xilinx-ISE and synthesized on hardware platform. The Performance parameters are tabulated for TFI-FTS based asynchronous circuits. The performance of TFI-FTS Module is analyzed with 100% fault coverage. The fault coverage is validated using functional simulation of each asynchronous circuit with fault injection in TFI-FTS Module.

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