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International Journal of Electrical and Computer Engineering

IJECE
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Published by Institute of Advanced Engineering and Science

ISSN : 20888708 EISSN : 27222578 DOI : -

Core Subject : Science, Engineering,

Computer Science & IT Electrical & Electronics Engineering

International Journal of Electrical and Computer Engineering (IJECE, ISSN: 2088-8708, a SCOPUS indexed Journal, SNIP: 1.001; SJR: 0.296; CiteScore: 0.99; SJR & CiteScore Q2 on both of the Electrical & Electronics Engineering, and Computer Science) is the official publication of the Institute of Advanced Engineering and Science (IAES). The journal is open to submission from scholars and experts in the wide areas of electrical, electronics, instrumentation, control, telecommunication and computer engineering from the global world.

Arjuna Subject : Ilmu Komputer (semua kategori) - Ilmu Komputer (Lain-Lain)

Articles 67 Documents

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Search results for , issue "Vol 7, No 4: August 2017" : 67 Documents clear

FPGA-based Design System for a Two-Segment Fibonacci LFSR Random Number Generator Zulfikar Zulfikar; Yuwaldi Away; Rafiqa Shahnaz Noor
International Journal of Electrical and Computer Engineering (IJECE) Vol 7, No 4: August 2017
Publisher : Institute of Advanced Engineering and Science

For a long time, random numbers have been used in many fields of application. Much work has been conducted to generate truly random numbers and is still in progress. A popular method for generating random numbers is a linear-feedback shift register (LFSR). Even though a lot of work has been done using this method to search for truly random numbers, it is an area that continues to attract interest. Therefore, this paper proposes a circuit for generating random numbers. The proposed circuit is designed to produce different sequences of numbers. Two segments of Fibonacci LFSR are used to form a generator that can produce more varied random numbers. The proposed design consists of blocks: segment 1, segment 2, and a clock controller. The system produces random numbers based on an external clock. The clock signal for the first segment is that of the external clock, whereas that for the second segment is modified by the clock controller. The second stage (segment 2) is executed only after every 2n1−1 clock cycles. The proposed design can generate different sequences of random numbers compare to those of the conventional methods. The period of the proposed system is less than that of the original Fibonacci LFSR. However, the period is almost equal to the original one when the system is realized in 32-bit or 64-bit form. Finally, the proposed design is implemented on a field-programmable gate array (FPGA). It occupies more area and runs at a lower frequency compared with the original Fibonacci LFSR. However, the proposed design is more efficient than the segmented leap-ahead method concerning space occupancy.

A Simplified Speed Control of Induction Motor based on a Low Cost FPGA Lotfi charaabi; Ibtihel Jaziri
International Journal of Electrical and Computer Engineering (IJECE) Vol 7, No 4: August 2017
Publisher : Institute of Advanced Engineering and Science

This paper investigates the development of a simplified speed control of induction motor based on indirect field oriented control (FOC). An original PI-P controller is designed to obtain good performances for speed tracking. Controller coefficients are carried out with analytic approach. The algorithm is implemented using a low cost Field Programmable Gate Array (FPGA). The implementation is followed by an efficient design methodology that offers considerable design advantages. The main advantage is the design of reusable and reconfigurable hardware modules for the control of electrical systems. Experimental results carried on a prototyping platform are given to illustrate the efficiency and the benefits of the proposed approach.

Fuzzy Association Rule Mining based Model to Predict Students’ Performance Sushil Kumar Verma; R.S. Thakur; Shailesh Jaloree
International Journal of Electrical and Computer Engineering (IJECE) Vol 7, No 4: August 2017
Publisher : Institute of Advanced Engineering and Science

The major intention of higher education institutions is to supply quality education to its students. One approach to get maximum level of quality in higher education system is by discovering knowledge for prediction regarding the internal assessment and end semester examination. The projected work intends to approach this objective by taking the advantage of fuzzy inference technique to classify student scores data according to the level of their performance. In this paper, student’s performance is evaluated using fuzzy association rule mining that describes Prediction of performance of the students at the end of the semester, on the basis of previous database like Attendance, Midsem Marks, Previous semester marks and Previous Academic Records were collected from the student’s previous database, to identify those students which needed individual attention to decrease fail ration and taking suitable action for the next semester examination.

Extending UPnP for Application Interoperability in a Home Network Kalaiselvi Arunachalam; Gopinath Ganapathy
International Journal of Electrical and Computer Engineering (IJECE) Vol 7, No 4: August 2017
Publisher : Institute of Advanced Engineering and Science

The Universal Plug and Play (UPnP) technology offers pervasive communication across heterogeneous devices in a home or small office network. The UPnP specifications are available for devices only to be interoperable together in a home or small office network. This paper proposes an extension of the UPnP technology for application interoperability in a home or small office network. This paper provides an UPnP Application Architecture as an extension to the existing UPnP Device Architecture. This extension enhances the feature of UPnP from device interoperability to application interoperability which enables the applications to discover, control and share data with each other in a home or small office network despite of their device type and operating system. In addition to the UPnP Application Architecture, the UPnP Application Template and UPnP Application Service Template are defined towards the development of UPnP-enabled applications that run on heterogeneous devices in a home or small office network.

Single Channel Speech Enhancement using Wiener Filter and Compressive Sensing Amart Sulong; Teddy Surya Gunawan; Othman O Khalifa; Mira Kartiwi; Hassan Dao
International Journal of Electrical and Computer Engineering (IJECE) Vol 7, No 4: August 2017
Publisher : Institute of Advanced Engineering and Science

The speech enhancement algorithms are utilized to overcome multiple limitation factors in recent applications such as mobile phone and communication channel. The challenges focus on corrupted speech solution between noise reduction and signal distortion. We used a modified Wiener filter and compressive sensing (CS) to investigate and evaluate the improvement of speech quality. This new method adapted noise estimation and Wiener filter gain function in which to increase weight amplitude spectrum and improve mitigation of interested signals. The CS is then applied using the gradient projection for sparse reconstruction (GPSR) technique as a study system to empirically investigate the interactive effects of the corrupted noise and obtain better perceptual improvement aspects to listener fatigue with noiseless reduction conditions. The proposed algorithm shows an enhancement in testing performance evaluation of objective assessment tests outperform compared to other conventional algorithms at various noise type conditions of 0, 5, 10, 15 dB SNRs. Therefore, the proposed algorithm significantly achieved the speech quality improvement and efficiently obtained higher performance resulting in better noise reduction compare to other conventional algorithms.

New Realization of Quadrature Oscillator using OTRA Gurumurthy Komanaplli; Neeta Pandey; Rajeshwari Pandey
International Journal of Electrical and Computer Engineering (IJECE) Vol 7, No 4: August 2017
Publisher : Institute of Advanced Engineering and Science

In this paper a new, operational transresistance amplifier (OTRA) based, third order quadrature oscillator (QO) is presented. The proposed structure forms a closed loop using a high pass filter and differentiator. All the resistors employed in the circuit can be implemented using matched transistors operating in linear region thereby making the proposed structure fully integrated and electronically tunable. The effect of non-idealities of OTRA has been analyzed which suggests that for high frequency applications self-compensation can be used. Workability of the proposed QO is verified through SPICE simulations using 0.18μm AGILENT CMOS process parameters. Total harmonic distortion (THD) for the proposed QO is found to be less than 2.5%.The sensitivity, phasenoise analysis is also discussed for the proposed structure.

Particle Swarm Optimization for the Path Loss Reduction in Suburban and Rural Area Messaoud Garah; Houcine Oudira; Lotfi Djouane; Nazih Hamdiken
International Journal of Electrical and Computer Engineering (IJECE) Vol 7, No 4: August 2017
Publisher : Institute of Advanced Engineering and Science

In the present work, a precise optimization method is proposed for tuning the parameters of the COST231 model to improve its accuracy in the path loss propagation prediction. The Particle Swarm Optimization is used to tune the model parameters. The predictions of the tuned model are compared with the most popular models. The performance criteria selected for the comparison of various empirical path loss models is the Root Mean Square Error (RMSE). The RMSE between the actual and predicted data are calculated for various path loss models. It turned out that the tuned COST 231 model outperforms the other studied models.

A New Induction Motor Adaptive Robust Vector Control based on Backstepping Mhamed Madark; A. Ba-Razzouk; E. Abdelmounim; M.El Malah
International Journal of Electrical and Computer Engineering (IJECE) Vol 7, No 4: August 2017
Publisher : Institute of Advanced Engineering and Science

In this paper, a novel approach to nonlinear control of induction machine, recursive on-line estimation of rotor time constant and load torque are developed. The proposed strategy combines Integrated Backstepping and Indirect Field Oriented Controls. The proposed approach is used to design controllers for the rotor flux and speed, estimate the values of rotor time constant and load torque and track their changes on-line. An open loop estimator is used to estimate the rotor flux. Simulation results are presented which demonstrate the effectiveness of the control technique and on-line estimation.

Security Enhancement in Networked Embedded System Pradip Ram Selokar; P T Karule
International Journal of Electrical and Computer Engineering (IJECE) Vol 7, No 4: August 2017
Publisher : Institute of Advanced Engineering and Science

In the developed system ARM9 is a master and Two ARM7s are slaves. The peripherals are being controlled by two ARM7 boards. The Peripherals are connected to the ARM7 through Complex Programmable Logic Device (CPLD). The CPLD is in turn connected to the ARM7 using Serial Peripheral Interface (SPI). The ARM7 boards collect the information from the peripherals and send it to the ARM9 board. The communication between ARM7 and ARM9 is via UART (Universal Asynchronous Receiver Transmitter) over CAN (Controller Area Network). The ARM9 board has got the software intelligence. The ARM9 behaves as a master and two ARM7 boards behave as slaves. Being master ARM9 passes tokens to ARM7 which in turn returns (Acknowledges) the token. The ARM9 is further connected to Proxy via Ethernet. The proxy is further connected to the service platform (server) via Ethernet. So subsequently any decisions at any stage can be changed at server level. Further these commands can be passed on to ARM9 which in turn controls the peripherals through ARM7. (a) The system which we have developed consists of ARM9 as a master, Two ARM7 as Slaves. The communication between ARM9-ARM7 is via UART over a CAN, (b) Each ARM7 further communicates serially (RS232) with the two 8051 Microcontroller nodes, (c)Thus a networked Embedded System is developed wherein the serial data is brought over Ethernet. The ARM7 board, which is directly linked with the peripherals, can be modified of its functionality as and when required. The functionality of ARM7 can be modified by upgrading its firmware. To upgrade the firmware same communication link has been used. ARM7 receives the new firmware via same ARM9-ARM7 communication link. The Flash Write operation is performed using the source code to write the new firmware. Bootloader application for the ARM7 has been developed. The signature has been incorporated to assure authenticity of the new Firmware. Intel Hex File Format is used to parse the hex file.

Performance Analysis of 3-Level 5-Phase Multilevel Inverter Topologies B. Jyothi; M. Venu Gopala Rao
International Journal of Electrical and Computer Engineering (IJECE) Vol 7, No 4: August 2017
Publisher : Institute of Advanced Engineering and Science

Now a day’s many industrial applications requires high power. Some other appliances may require intermediate power either more or less depending upon their operation. With these consequences, MULTI LEVEL INVERTERS are introduced in 1975.for above intermediate voltage applications. The name MULTI LEVEL began with the three-level converter.By enormous advancement in power semiconductor switches, in electric drives increasing the phase number greater than the conventional three phase especially in locomotives, naval, aerospace, and electrical vehicles industry has many advantages than three phase. In this view, here five phase VSI has developed. This paper aims at comparing the performance of conventional two level inverter Diode clamped and Capacitor clamped topologies of 5-phase multilevel inverter (3-level) using sinusoidal pulse width modulation. SPWM is highly economical, has more efficiency, controllability. These circuits are analyzed by using simulation software package such as MATLAB.

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Tole Sutikno

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ijece@iaesjournal.com

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ijece@iaesjournal.com

Editorial Address
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Location
Kota yogyakarta,

Daerah istimewa yogyakarta

INDONESIA

Abstract

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Home Page

OAI Link

Editorial Team

Contact

Reviewer

Google Scholar

Contact Name Tole Sutikno

Contact Email ijece@iaesjournal.com

Phone -

Journal Mail Official ijece@iaesjournal.com

Editorial Address -

Location Kota yogyakarta, Daerah istimewa yogyakarta INDONESIA

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Contact Name
Tole Sutikno

Contact Email
ijece@iaesjournal.com

Phone
-

Journal Mail Official
ijece@iaesjournal.com

Editorial Address
-

Location
Kota yogyakarta,

Daerah istimewa yogyakarta

INDONESIA