International Journal of Electrical and Computer Engineering			
            
            
            
            
            
            
            
            International Journal of Electrical and Computer Engineering (IJECE, ISSN: 2088-8708, a SCOPUS indexed Journal, SNIP: 1.001; SJR: 0.296; CiteScore: 0.99; SJR & CiteScore Q2 on both of the Electrical & Electronics Engineering, and Computer Science) is the official publication of the Institute of Advanced Engineering and Science (IAES). The journal is open to submission from scholars and experts in the wide areas of electrical, electronics, instrumentation, control, telecommunication and computer engineering from the global world.
            
            
         
        
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                            MalayIK: An Ontological Approach to Knowledge Transformation in Malay Unstructured Documents 
                        
                        Fatimah Sidi; 
Iskandar Ishak; 
Marzanah A. Jabar                        
                         International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 1: February 2018 
                        
                        Publisher : Institute of Advanced Engineering and Science 
                        
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                                    DOI: 10.11591/ijece.v8i1.pp1-10                                
                                                    
                        
                            
                                
                                
                                    
The number of unstructured documents written in Malay language is enormously available on the web and intranets. However, unstructured documents cannot be queried in simple ways, hence the knowledge contained in such documents can neither be used by automatic systems nor could be understood easily and clearly by humans. This paper proposes a new approach to transform extracted knowledge in Malay unstructured document using ontology by identifying, organizing, and structuring the documents into an interrogative structured form. A Malay knowledge base, the MalayIK corpus is developed and used to test the MalayIK-Ontology against Ontos, an existing data extraction engine. The experimental results from MalayIK-Ontology have shown a significant improvement of knowledge extraction over Ontos implementation. This shows that clear knowledge organization and structuring concept is able to increase understanding, which leads to potential increase in sharable and reusable of concepts among the community.
                                
                             
                         
                     
                    
                                            
                        
                            A Simplified Design and Modeling of Boost Converter for Photovoltaic Sytem 
                        
                        Arjyadhara Pradhan; 
Bhagabat Panda                        
                         International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 1: February 2018 
                        
                        Publisher : Institute of Advanced Engineering and Science 
                        
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                                    DOI: 10.11591/ijece.v8i1.pp141-149                                
                                                    
                        
                            
                                
                                
                                    
The Photovoltaic standalone system is gaining its high importance mostly for rural application like pv water pumping, solar lighting, battery charging etc.Considering environmental effects and scarcity of fossil fuel the trend has developed towards the use of more and more renewable energy.In this paper a basic circuit of boost converter is designed in MATLAB/Simulink with constant dc source voltage. However a comparative study has also been done for the converter connected with pv system directly with the converter connected with mppt tracking technique. Perturb and Observance (P&O) algorithm is implemented for providing the necessary duty pulse and makes the system operate at maximum power point.The boost converter connected with PV system without mppt operates at any other point other then the maximum power point and hence the output voltage decreases.But with mppt the proposed system performs better.
                                
                             
                         
                     
                    
                                            
                        
                            Performances Concatenated LDPC based STBC-OFDM System and MRC Receivers 
                        
                        Nejwa El Maammar; 
Seddik Bri; 
Jaouad Foshi                        
                         International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 1: February 2018 
                        
                        Publisher : Institute of Advanced Engineering and Science 
                        
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                                    DOI: 10.11591/ijece.v8i1.pp622-630                                
                                                    
                        
                            
                                
                                
                                    
This paper presents the bit error rate performance of the low density parity check (LDPC) with the concatenation of convolutional channel coding based orthogonal frequency-division-multiplexing (OFDM) using space time block coded (STBC). The OFDM wireless communication system incorporates 3/4-rated convolutional encoder under various digital modulations (BPSK, QPSK and QAM) over an additative white gaussian noise (AWGN) and fading (Raleigh and Rician) channels. At the receiving section of the simulated system, Maximum Ratio combining (MRC) channel equalization technique has been implemented to extract transmitted symbols without enhancing noise power.
                                
                             
                         
                     
                    
                                            
                        
                            A Framework for Optimizing the Process of Energy Harvesting from Ambient RF Sources 
                        
                        Ruchi Sharma; 
S. Balaji                        
                         International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 1: February 2018 
                        
                        Publisher : Institute of Advanced Engineering and Science 
                        
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                                    DOI: 10.11591/ijece.v8i1.pp450-457                                
                                                    
                        
                            
                                
                                
                                    
Energy harvesting has been an active research topic in the past half a decade with respect to wireless networks. We reviewed some of the recent techniques towards improving energy harvesting performance to find that there is a large scope of improvement in terms of optimization and addressing problems pertaining to low-powered communicating mobile nodes. Therefore, we present a framework for identifying available RF sources of energy and constructing a robust link between the energy source and the mobile device. We apply linear optimization approach to enhance the performance of energy harvesting. Probabilility theory is used for identification of event loss in the presence of different number of nodes as well as node distances. The objective of the proposed system is to offer better availability of RF signals as well as better probability of energy harvesting for mobile devices. The proposed technique is also found to be computationally cost effective.
                                
                             
                         
                     
                    
                                            
                        
                            A Sense-based Registration Process for TDMA in IEEE 802.11 Network 
                        
                        Rizal Fathoni Aji; 
Heru Suhartanto; 
Setiadi Yazid                        
                         International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 1: February 2018 
                        
                        Publisher : Institute of Advanced Engineering and Science 
                        
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                                    DOI: 10.11591/ijece.v8i1.pp355-359                                
                                                    
                        
                            
                                
                                
                                    
TDMA implementation offer better fairness and throughput in IEEE 802.11. To implement TDMA, new registration process is needed, because current registration mechanism can disrupt TDMA process. This paper proposes a sense-based TDMA registration process using service slot and random timer. Simulation result shows, by using our mechanism, we can reduce the number of unused timeslot, and for 10 new nodes, each node only need 7 ms to complete the registration process.
                                
                             
                         
                     
                    
                                            
                        
                            The Indonesia Public Information Disclosure Act (UU-KIP): Its Challenges and Responses 
                        
                        Muharman Lubis; 
Tien Fabrianti Kusumasari; 
Lukmanul Hakim                        
                         International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 1: February 2018 
                        
                        Publisher : Institute of Advanced Engineering and Science 
                        
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                                    DOI: 10.11591/ijece.v8i1.pp94-103                                
                                                    
                        
                            
                                
                                
                                    
Information Public Disclosure is one of the regulation that has purpose to encourage good governance for public service and citizen participation in national development. The enactment of Act No.14/2008 (UU KIP) has been strengthen the mandate to enforce the necessity of information disclosure in actualizing transparency and accountability in resource management and budget uses. It also become the primary instrument to prevent corruption, monopolistic competition and information disputes. However, there are certain provinces has not yet established information committee nor when it will be as entrusted by the regulation. Meanwhile, the remedies in term of jail duration and fines, arguably, it could not create deterrent effect to the perpetrator. Furthermore, the concern from ministry and public institution also in question in regard their roles of responsibility, lack of cooperation and continuous support. Thus, human resource, technology infrastructure, public participation, supervision and socialization become crucial factor to increase the awareness and satisfaction towards this regulatory compliance. This study is a qualitative research to evaluate the implementation of this Act by observing its consideration, background, principles and relevant article verses as primary sources through content analysis based on number of legal experts.
                                
                             
                         
                     
                    
                                            
                        
                            Traffic Light Signal Parameters Optimization using Modification of Multielement Genetic Algorithm 
                        
                        I Gede Pasek Suta Wijaya; 
Keeichi Uchimura; 
Gou Koutaki                        
                         International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 1: February 2018 
                        
                        Publisher : Institute of Advanced Engineering and Science 
                        
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                                    DOI: 10.11591/ijece.v8i1.pp246-253                                
                                                    
                        
                            
                                
                                
                                    
A strategy to optimize traffic light signal parameters is presented for solving traffic congestion problem using modification of the Multielement Genetic Algorithm (MEGA). The aim of this method is to improve the lack of vehicle throughput (FF ) of the works called as traffic light signal parameters optimization using the MEGA and Particle Swarm Optimization (PSO). In this case, the modification of MEGA is done by adding Hash-Table for saving some best populations for accelerating the recombination process of MEGA which is shortly called as H-MEGA. The experimental results show that the H-MEGA based optimization provides better performance than MEGA and PSO based methods (improving the FF of both MEGA and PSO based optimization methods by about 10.01% (from 82,63% to 92.64%) and 6.88% (from 85.76% to 92.64%), respectively). In addition, the H-MEGA improve significantly the real FF of Ooe Toroku road network of Kumamoto City, Japan about 21.62%.
                                
                             
                         
                     
                    
                                            
                        
                            Virtual Machine Allocation Policy in Cloud Computing Environment using CloudSim 
                        
                        Taskeen Zaidi; 
Rampratap Rampratap                        
                         International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 1: February 2018 
                        
                        Publisher : Institute of Advanced Engineering and Science 
                        
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                                    DOI: 10.11591/ijece.v8i1.pp344-354                                
                                                    
                        
                            
                                
                                
                                    
Cloud computing has been widely accepted by the researchers for the web applications. During the past years, distributed computing replaced the centralized computing and finally turned towards the cloud computing. One can see lots of applications of cloud computing like online sale and purchase, social networking web pages, country wide virtual classes, digital libraries, sharing of pathological research labs, supercomputing and many more. Creating and allocating VMs to applications use virtualization concept. Resource allocates policies and load balancing polices play an important role in managing and allocating resources as per application request in a cloud computing environment. Cloud analyst is a GUI tool that simulates the cloud-computing environment. In the present work, the cloud servers are arranged through step network and a UML model for a minimization of energy consumption by processor, dynamic random access memory, hard disk, electrical components and mother board is developed. A well Unified Modeling Language is used for design of a class diagram. Response time and internet characteristics have been demonstrated and computed results are depicted in the form of tables and graphs using the cloud analyst simulation tool.
                                
                             
                         
                     
                    
                                            
                        
                            Emotion Recognition from Facial Expression Based on Fiducial Points Detection and using Neural Network 
                        
                        Fatima Zahra Salmam; 
Abdellah Madani; 
Mohamed Kissi                        
                         International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 1: February 2018 
                        
                        Publisher : Institute of Advanced Engineering and Science 
                        
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                                    DOI: 10.11591/ijece.v8i1.pp52-59                                
                                                    
                        
                            
                                
                                
                                    
The importance of emotion recognition lies in the role that emotions play in our everyday lives. Emotions have a strong relationship with our behavior. Thence, automatic emotion recognition, is to equip the machine of this human ability to analyze, and to understand the human emotional state, in order to anticipate his intentions from facial expression. In this paper, a new approach is proposed to enhance accuracy of emotion recognition from facial expression, which is based on input features deducted only from fiducial points. The proposed approach consists firstly on extracting 1176 dynamic features from image sequences that represent the proportions of euclidean distances between facial fiducial points in the first frame, and faicial fiducial points in the last frame. Secondly, a feature selection method is used to select only the most relevant features from them. Finally, the selected features are presented to a Neural Network (NN) classifier to classify facial expression input into emotion. The proposed approach has achieved an emotion recognition accuracy of 99% on the CK+ database, 84.7% on the Oulu-CASIA VIS database, and 93.8% on the JAFFE database.
                                
                             
                         
                     
                    
                                            
                        
                            Reversed-Trellis Tail-Biting Convolutional Code (RT-TBCC) Decoder Architecture Design for LTE 
                        
                        Trio Adiono; 
Ahmad Zaky Ramdani; 
Rachmad Vidya Wicaksana Putra                        
                         International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 1: February 2018 
                        
                        Publisher : Institute of Advanced Engineering and Science 
                        
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                                    DOI: 10.11591/ijece.v8i1.pp198-209                                
                                                    
                        
                            
                                
                                
                                    
Tail-biting convolutional codes (TBCC) have been extensively applied in communication systems. This method is implemented by replacing the fixed-tail with tail-biting data. This concept is needed to achieve an effective decoding computation. Unfortunately, it makes the decoding computation becomes more complex. Hence, several algorithms have been developed to overcome this issue in which most of them are implemented iteratively with uncertain number of iteration. In this paper, we propose a VLSI architecture to implement our proposed reversed-trellis TBCC (RT-TBCC) algorithm. This algorithm is designed by modifying direct-terminating maximum-likelihood (ML) decoding process to achieve better correction rate. The purpose is to offer an alternative solution for tail-biting convolutional code decoding process with less number of computation compared to the existing solution. The proposed architecture has been evaluated for LTE standard and it significantly reduces the computational time and resources compared to the existing direct-terminating ML decoder. For evaluations on functionality and Bit Error Rate (BER) analysis, several simulations, System-on-Chip (SoC) implementation and synthesis in FPGA are performed.