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International Journal of Electrical and Computer Engineering
ISSN : 20888708     EISSN : 27222578     DOI : -
International Journal of Electrical and Computer Engineering (IJECE, ISSN: 2088-8708, a SCOPUS indexed Journal, SNIP: 1.001; SJR: 0.296; CiteScore: 0.99; SJR & CiteScore Q2 on both of the Electrical & Electronics Engineering, and Computer Science) is the official publication of the Institute of Advanced Engineering and Science (IAES). The journal is open to submission from scholars and experts in the wide areas of electrical, electronics, instrumentation, control, telecommunication and computer engineering from the global world.
Articles 6,301 Documents
Field Oriented Control of PMSM Supplied by Photovoltaic Source Mehimmedetsi Boudjemaa; Chenni Rachid
International Journal of Electrical and Computer Engineering (IJECE) Vol 6, No 3: June 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (463.897 KB) | DOI: 10.11591/ijece.v6i3.pp1233-1247

Abstract

The Permanent magnet synchronous motor (PMSM) is suitable for so much application, such as traction, aeronautics and generally in industrial automated processes. In our work, we will study the application of PMSM in renewable energies especially solar pumping. Our objective is to model the complete system, including the photovoltaic inverter, PMSM and the centrifugal pump under Matlab/Simulink environment. Solar panels generate electrical energy as direct current by direct conversion of solar radiation using semiconductor materials made of monocrystalline, polycrystalline or amorphous silicon. The energy received depends on radiation and on ambient temperature. The permanent magnet synchronous motor (PMSM) is not stable in open loop. To control the PMSM in terms of speed, torque or position, we need to implement vector control.We will establish the field oriented control of a PMSM supplied by photovoltaic source with a focus on their applications in variable speed domain.
State Space Modeling and Small Signal Stability Analysis of Synchronous Generator with Fuzzy based AVR Ramya R; Selvi K
International Journal of Electrical and Computer Engineering (IJECE) Vol 2, No 6: December 2012
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (280.368 KB)

Abstract

This paper presents a linear mathematical model of a Synchronous Generator with excitation system for small signal stability analysis. This work aims to develop a controller based on fuzzy logic to simulate an Automatic Voltage Regulator (AVR) for a synchronous generator. The performance of fuzzy based AVR is tested on Single Machine connected to an Infinite Bus bar system (SMIB) in the MATLAB/SIMULINK platform and the results are compared with the IEEE Exciter model.DOI:http://dx.doi.org/10.11591/ijece.v2i6.1524
Impedance Matching Method in Two-Stage Converters for Single Phase PV-Grid System L. Heru Pratomo; F. Danang Wijaya; Eka Firmansyah
International Journal of Electrical and Computer Engineering (IJECE) Vol 5, No 4: August 2015
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (325.4 KB) | DOI: 10.11591/ijece.v5i4.pp626-635

Abstract

This paper presents the study on the impedance matching method in two-stage converters for single phase PV-grid system. The use of PV systems was to obtain the electrical power from the sunlight energy. The system consisted of a Buck-Boost DC-DC converter and a five-level inverter. A Buck-Boost DC-DC converter was used as a means of impedance matching to obtain the maximum power that, in this case, through a method by using the incremental conductance current control algorithm. Meanwhile a five-level inverter was used as an interface to the utilities.  By using this technique, the system came to be simple. The impedance of the power grid, a Buck-Boost DC-DC converter, and a five-level inverter were seen by PV mostly in the area of RMPP, enabling the maximum power produced by the PV to be delivered to the grid. To demonstrate the effectiveness of the design, the analysis and simulation results, furthermore, were provided
A Prolific Scheme for Load Balancing Relying on Task Completion Time V. Anand; K. Anuradha
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 3: June 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (177.502 KB) | DOI: 10.11591/ijece.v8i3.pp1741-1746

Abstract

In networks with lot of computation, load balancing gains increasing significance. To offer various resources, services and applications, the ultimate aim is to facilitate the sharing of services and resources on the network over the Internet. A key issue to be focused and addressed in networks with large amount of computation is load balancing. Load is the number of tasks‘t’ performed by a computation system. The load can be categorized as network load and CPU load. For an efficient load balancing strategy, the process of assigning the load between the nodes should enhance the resource utilization and minimize the computation time. This can be accomplished by a uniform distribution of load of to all the nodes. A Load balancing method should guarantee that, each node in a network performs almost equal amount of work pertinent to their capacity and availability of resources. Relying on task subtraction, this work has presented a pioneering algorithm termed as E-TS (Efficient-Task Subtraction). This algorithm has selected appropriate nodes for each task. The proposed algorithm has improved the utilization of computing resources and has preserved the neutrality in assigning the load to the nodes in the network.
Finding a suitable threshold value for an iris-based authentication system Narongrit Wangkeeree; Sirapat Boonkrong
International Journal of Electrical and Computer Engineering (IJECE) Vol 9, No 5: October 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (808.993 KB) | DOI: 10.11591/ijece.v9i5.pp3558-3568

Abstract

Authentication is the first line of defense of any information technology systems. One of the popular methods used today is biometric, and iris authentication is gaining popularity. However, the threshold value is deemed to be secure and appropriate has not been thoroughly studied. Threshold is a value that defines the acceptable amount of the correct bits of the image before securely passing the authentication process. Therefore, the main aim of this research was to find a secure and suitable threshold value used in iris authentication system, where iris localization was done by using Circle Hough Transform technique. Iris image databases v.4 from the Chinese Academy of Sciences Institute of Automatic (CASIA) were used in this research. The way to find the appropriate threshold was to test for the right balance of the GAR, FRR and FAR values when trying to verify the person’s identity. The results of the test revealed that the appropriate threshold had the value of 72.9246 percent of all the available bits of the iris image. Both had a high GAR and very low FAR and FRR values.  It can be concluded that the obtained threshold value was suitable and secure.
Parallel Genetic Algorithms for University Scheduling Problem Artan Berisha; Eliot Bytyçi; Ardeshir Tershnjaku
International Journal of Electrical and Computer Engineering (IJECE) Vol 7, No 2: April 2017
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (1244.806 KB) | DOI: 10.11591/ijece.v7i2.pp1096-1102

Abstract

University scheduling timetabling problem, falls into NP hard problems. Re-searchers have tried with many techniques to find the most suitable and fastest way for solving the problem. With the emergence of multi-core systems, the parallel implementation was considered for finding the solution. Our approaches attempt to combine several techniques in two algorithms: coarse grained algorithm and multi thread tournament algorithm. The results obtained from two algorithms are compared, using an algorithm evaluation function. Considering execution time, the coarse grained algorithm performed twice better than the multi thread algorithm.
The conceptual model of information confrontation of virtual communities in social networking services Kateryna Molodetska; Yuriy Tymonin; Ihor Melnychuk
International Journal of Electrical and Computer Engineering (IJECE) Vol 10, No 1: February 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (677.886 KB) | DOI: 10.11591/ijece.v10i1.pp1043-1052

Abstract

Social networking services are one of the most popular mass media and are used as an effective tool for information confrontation due to their functional characteristics. Existing models of information confrontation take into account the redistribution between conflict parties of only one kind of resource, although in the social networking services there is a need to consider additional factors that determine the effectiveness of virtual communities’ opposition. A conceptual model of information confrontation of virtual communities in social networking services has been developed, and it includes three-layer dynamics of the number of actors, growth of information resources of virtual communities and dynamics of spending resources for the confrontation conduct. The model also takes into account the peculiarities of the antagonistic conflict of virtual communities’ actors through the choice of a differential equation that corresponds to the type of its dynamics. The offered conceptual model formalizes the behavior of virtual communities’ actors in the conditions of antagonistic conflict. At the same time, it allows to investigate the peculiarities of using different strategies to carry out the information fight of virtual communities in social networking services, to choose optimal strategies, to predict the development of conflicts in the information space and to develop effective measures to counter threats to the state’s information security.
Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction Techniques Anil Khatak; Manoj Kumar; Sanjeev Dhull
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 6: December 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (539.412 KB) | DOI: 10.11591/ijece.v8i6.pp4922-4931

Abstract

To reduce power consumption of regenerative comparator three different techniques are incorporated in this work. These techniques provide a way to achieve low power consumption through their mechanism that alters the operation of the circuit. These techniques are pseudo NMOS, CVSL (cascode voltage switch logic)/DCVS (differential cascode voltage switch) & power gating. Initially regenerative comparator is simulated at 90 nm CMOS technology with 0.7 V supply voltage. Results shows total power consumption of 15.02 μW with considerably large leakage current of 52.03 nA. Further, with pseudo NMOS technique total power consumption increases to 126.53 μW while CVSL shows total power consumption of 18.94 μW with leakage current of 1270.13 nA. More then 90% reduction is attained in total power consumption and leakage current by employing the power gating technique. Moreover, the variations in the power consumption with temperature is also recorded for all three reported techniques where power gating again show optimum variations with least power consumption. Four more conventional comparator circuits are also simulated in 90nm CMOS technology for comparison. Comparison shows better results for regenerative comparator with power gating technique. Simulations are executed by employing SPICE based on 90 nm CMOS technology.
Replacement of Analog Automatic Voltage Regulator using Digital Technology Ersalina Werda Mukti; Sulistyo Wijanarko; Anwar Muqorobin
International Journal of Electrical and Computer Engineering (IJECE) Vol 6, No 1: February 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (355.925 KB) | DOI: 10.11591/ijece.v6i1.pp53-62

Abstract

Before the 90’s, many power plants in Indonesia were equipped with analog controllers and now those power plants are still in operation to produce electricity. One of those controller parts is Automatic Voltage Regulator (AVR). If a failure occurs in the AVR, the economic solution is by replacing the damaged electronic component with new component. However this method will not solve the problem if the components are not available in local market or become obsolete. Purchasing the new AVR that compatible with other controller parts cannot be done again because the analog controllers are no longer produced by the vendor. Furthermore, replacement of all the controllers with the current technology become expensive.  According to this, an alternative solution is proposed in this paper by designing an AVR that compatible with other controller parts and considering the availability of the electronic components in local market. ATmega8 microcontroller is used to implement a digital AVR and employing op amp based as its signal conditioning. The result shows that the digital AVR can reduce hardware size and power consumption. The digital AVR also meets the computation rate of the computation signal.
An Influence of Measurement Scale of Predictor Variable on Logistic Regression Modeling and Learning Vector Quntization Modeling for Object Classification Waego Hadi Nugroho; Samingun Handoyo; Yusnita Julyarni Akri
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 1: February 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (484.02 KB) | DOI: 10.11591/ijece.v8i1.pp333-343

Abstract

Much real world decision making is based on binary categories of information that agree or disagree, accept or reject, succeed or fail and so on. Information of this category is the output of a classification method that is the domain of statistical field studies (eg Logistic Regression method) and machine learning (eg Learning Vector Quantization (LVQ)). The input argument of a classification method has a very crucial role to the resulting output condition. This paper investigated the influence of various types of input data measurement (interval, ratio, and nominal) to the performance of logistic regression method and LVQ in classifying an object. Logistic regression modeling is done in several stages until a model that meets the suitability model test is obtained. Modeling on LVQ was tested on several codebook sizes and selected the most optimal LVQ model. The best model of each method compared to its performance on object classification based on Hit Ratio indicator. In logistic regression model obtained 2 models that meet the model suitability test is a model with predictive variables scaled interval and nominal, while in LVQ modeling obtained 3 pieces of the most optimal model with a different codebook. In the data with interval-scale predictor variable, the performance of both methods is the same. The performance of both models is just as bad when the data have the predictor variables of the nominal scale. In the data with predictor variable has ratio scale, the LVQ method able to produce moderate enough performance, while on logistic regression modeling is not obtained the model that meet model suitability test. Thus if the input dataset has interval or ratio-scale predictor variables than it is preferable to use the LVQ method for modeling the object classification.

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