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International Journal of Reconfigurable and Embedded Systems (IJRES)
Published by Institute of Advanced Engineering and Science
ISSN : 20894864     EISSN : 27222608     DOI : -
Core Subject : Economy,
Economics, Econometrics & Finance
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Arjuna Subject : -
Articles 16 Documents
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Search results for , issue "Vol 12, No 2: July 2023" : 16 Documents clear
Turbo encoder and decoder chip design and FPGA device analysis for communication system Aakanksha Devrari; Adesh Kumar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp174-185

Abstract

Turbo codes are error-correcting codes with performance that is close to the Shannon theoretical limit (SHA). The motivation for using turbo codes is that the codes are an appealing mix of a random appearance on the channel and a physically realizable decoding structure. The communication systems have the problem of latency, fast switching, and reliable data transfer. The objective of the research paper is to design and turbo encoder and decoder hardware chip and analyze its performance. Two convolutional codes are concatenated concurrently and detached by an interleaver or permuter in the turbo encoder. The expected data from the channel is interpreted iteratively using the two related decoders. The soft (probabilistic) data about an individual bit of the decoded structure is passed in each cycle from one elementary decoder to the next, and this information is updated regularly. The performance of the chip is also verified using the maximum a posteriori (MAP) method in the decoder chip. The performance of field-programmable gate array (FPGA) hardware is evaluated using hardware and timing parameters extracted from Xilinx ISE 14.7. The parallel concatenation offers a better global rate for the same component code performance, and reduced delay, low hardware complexity, and higher frequency support.
Development of magnetic levitation system with position and orientation control Siti Juliana Abu Bakar; Koay J-Shenn; Patrick Goh; Nur Syazreen Ahmad
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp287-296

Abstract

This work demonstrates the design and development of a magnetic levitation (MagLev) system that is able to control both the position and orientation of the levitated object. For the position control, a pole placement method was exploited to estimate parameters of the proportional integral derivative (PID) controller. In addition, the MagLev was constructed using a pair of electromagnets, two infrared (IR) receiver-emitter pairs and a servo motor to allow the orientation of the object to be controlled. The proposed controller was programmed in a LabVIEW environment, which was then compiled and deployed into an embedded NI myRIO board. Experimental results demonstrated that the proposed method was able to achieve a zero steady-state orientation error when the object was rotated from 0 ◦ to ±90◦ , a steady-state position error of 0.3 cm without rotation, and steady-state position errors of no greater than 1.2 cm with rotation.
Automated ventilator prototype for COVID-19 patient treatment: the design and development of the electronic system Adrián Stacul; Daniel Pastafiglia; Ariel Dalmas Di Giovanni; Martín Morales; Sergio Saluzzi; Gerardo García
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp222-229

Abstract

The coronavirus disease 2019 (COVID-19) pandemic has created an urgent global demand for ventilators, respirators and various resuscitation devices. Various research and development organizations, private companies and individual engineers have collaborated and carried out the development of low-cost ventilation prototypes. In turn, doctors and nurses are collapsed due to the exponential increase in COVID-19 cases. This scenario worsens more when the tasks are manual in nature. The article`s objective to describe the electronic system designed, developed and implemented in a functional prototype of an automatic ventilator in order to be evaluated by a team of health professionals to be later used in cases of health emergencies. This system automates the manual ventilation task aided by a few medical resources in a scenario of scarce resources and is a temporary solution when a respirator is not available.
S11 parameter results comparison in reconfigurable antennas under simulation and measurement V. Reji; C. T. Manimegalai
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp186-194

Abstract

In this paper, a simulation and measurement return loss parameter results comparison in frequency reconfigurable antenna is proposed. More lowprofile and compact microstrip antennas have been developed in recent years for 5 GHz, 5G, WLAN, Wi-Fi, and ISM band applications. These antenna frequency bands may be single, dual, or multiband. The small microstrip antenna, without connecting any external devices like switches, resonators, and passive elements, does not show any variations in their simulation and measurement results like return loss (S11 parameter), gain, and efficiency. However, in the S11 parameter most frequency reconfigurable antennas show a mismatch between simulation and measurement results. The reason for this mismatch between the simulation and measurement results are given in the paper.
Heart failure prediction based on random forest algorithm using genetic algorithm for feature selection Yudi Ramdhani; Cakra Mahendra Putra; Doni Purnama Alamsyah
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp205-214

Abstract

A disorder or illness called heart failure results in the heart becoming weak or damaged. In order to avoid heart failure early on, it is crucial to understand the causes of heart failure. Based on validation, two experimental processing steps will be applied to the dataset of clinical records related to heart failure. Testing will be done in the first step utilizing six different classification algorithms, including K-nearest neighbor, neural network, random forest, decision tree, Naïve Bayes, and support vector machine (SVM). Cross-validation was employed to conduct the test. According to the results, the random forest algorithm performed better than the other five algorithms in tests employing the algorithm. Subsequent testing uses an algorithm with the best accuracy value, which will then be tested again using split validation with varying split ratios and genetic algorithms as a selection feature. The value generated from testing using the genetic algorithm selection feature is better than the random forest algorithm alone, which is recorded to produce an accuracy value of 93.36% in predicting the survival of heart failure patients.
Research, challenges and opportunities in software define radio technologies Jacob Abraham; Kanagaraj Venusamy; Antony Judice; Joel Livin A. Obtained; Hameed Shaik; Kannadhasan Suriyan
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp260-268

Abstract

The network extended not just internationally but also throughout a broad variety of application areas in this age, with healthcare being one of the most well-known and vital industries. Improvements in healthcare are possible if we start using the popular internet of things (IoT) technology as a key instead of focusing on other disciplines. Wireless body area network (WBAN) is a field in which we communicate with a network of human people and medical equipment that may be used in conjunction with internet of things technology to perform any function. Additional features for software defined networks will be added in the future. In the event of a critical crisis, the suggested suggestions will be to take care of the patient's life. Because the fitted equipment keeps a lot better eye on the patient than previously advised methods. This study combines WBAN, IoT, and software defined network (SDN) to make sense in the healthcare field.
FPGA-based fault analysis for 7-level switched ladder multi-level inverter using decision tree algorithm Nithya Ramalingam; Anitha Thiagarajan
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp157-164

Abstract

The proposed method involves the fault analysis of the inverter switches present in the multi-level inverter (MLI) circuitry. The decision tree machine learning algorithm is incorporated for the fault analysis of the inverter switches. The multi-level inverter utilized in this work is a 7-level switched ladder multi-level inverter. There is 4 number of switches in the design of a 7-level inverter driven by the non-carrier digital pulse width modulation signals. The non-carried-based digital pulse-width modulator (DPWM) generation is generated using the event angle for the 7-level of the switched ladder inverter. The proposed method investigates the stuck-at-fault occurrences of the 4 switches in the inverter by manipulating the decision tree parameters such as entropy, information gain, and decision tree. Based on the decision tree, the very high-speed integrated circuit hardware description language (VHDL) code is developed by making use of the behavioral modeling and validated for the power, area in the Xilinx Vivado tool. The real-time feasibility is verified for the proposed method by synthesizing the developed VHDL code in the field programmable gate array (FPGA) device.
Analysis of frequency dependent Vedic chanting and its influence on neural activity of humans Veera Raghava Swamy Nalluri; V. J. K. Kishor Sonti; G. Sundari
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp230-239

Abstract

In this paper a novel methodology is proposed to identify and to compare the frequency range of different Vedic chantings from Rig Veda, Yajur Veda, Atharva Veda and Sama Veda. Nowadays in spite of busy schedule and hectic work, the human beings are mostly stressed. To get rid from this stressed state, one of the best solutions is listening Vedic chantings. The alpha brainwaves are in the frequency range of 8-12 Hz under giving relaxation to stressed human being. Three selected samples from each Veda have been processed through the simulation compiler Praat and the parameters like spectral response, pitch, intensity, formants and pulses have observed. In the above identified parameters, the frequency in intensity calculation is taken for each sample. This frequency is compared with the brainwaves for which the frequencies are in the ranges of 0 Hz to >27 Hz (alpha, beta, gamma, theta and delta). The extracted signal frequencies from Vedic chantings are compared with frequencies of brainwaves. Among the four Vedas, the frequencies extracted from Sama Veda lies in alpha frequency range. The remaining is fluctuating from alpha.
Video saliency-detection using custom spatiotemporal fusion method Warad, Vinay C.; Fatima, Ruksar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp269-275

Abstract

There have been several researches done in the field of image saliency but not as much as in video saliency. In order to increase precision and accuracy during compression, reduce coding complexity and time consumption along with memory allocation problems with our proposed solution. It is a modified high-definition video compression (HEVC) pixel based consistent spatiotemporal diffusion with temporal uniformity. It involves taking apart the video into groups of frames, computing colour saliency, integrate temporal fusion, pixel saliency fusion is conducted and then colour information guides the diffusion process for the spatiotemporal mapping with the help of permutation matrix. The proposed solution is tested on a publicly available extensive dataset with five global saliency valuation metrics and is compared with several other state-of-the-art saliency detection methods. The results display and overall best performance amongst all other candidates.
A novel reduced instruction set computer-communication processor design using field programmable gate array Joseph Anthony Prathap; Sai Ramesh
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp165-173

Abstract

In this paper, a novel reduced instruction set computer (RISC)- communication processor (RCP) has been designed with 32-bit operations which access 64-bit instruction format and implemented using field programmable gate array (FPGA). The design of the RISC processor is facilitated with communication operations like basic signals sine, cosine, and square, and modulation schemes like amplitude modulation, amplitude shift keying, analog, and digital quadrature amplitude modulation. Additionally, application-oriented operations like a traffic light, digital clock, and linear feedback shift register are included in the design. The pipeline mechanism is incorporated in the design to enhance the performance characteristics of the processor, hence allowing the execution of the instructions more effectively. Also, the design is implemented with Xilinx Virtex 7 family FPGA. The device utilization analysis of the proposed FPGA along with different FPGA families is evaluated and compared.

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