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International Journal of Reconfigurable and Embedded Systems (IJRES)

IJRES
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Published by Institute of Advanced Engineering and Science

ISSN : 20894864 EISSN : 27222608 DOI : -

Core Subject : Economy,

Economics, Econometrics & Finance

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.

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Articles 5 Documents

Search results for , issue "Vol 3, No 2: July 2014" : 5 Documents clear

FPGA Evaluation of Reconfigurable Modules With Fault Detection and Repair Technique Pradeep C; Radhakrishnan R
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 2: July 2014
Publisher : Institute of Advanced Engineering and Science

This paper proposes a fault detection and repair algorithm which is suitable for fault free reconfigurable systems. In recent years Built in Self Repair digital systems have got very important role in the applications such as nuclear systems, space missions and communication systems etc where system reliability is very critical . Systems designed to operate in critical conditions will collapse due to even a single fault occurrence. To avoid these situations many methods have developed in recent years. This work proposes an area efficient and fast fault detection and repair algorithm. For the evaluation of the new approach and older methods a system with a standalone module and four add on modules were designed and evaluated for resource utilization using XUPV5 board. The entire FPGA is divided in to tiles and each module is implemented in different tiles using partial reconfiguration method using Xilinx Plan Ahead 14.2 with partial reconfiguration facility.

Design of AES Algorithm for 128/192/256 Key Length in FPGA Pravin V. Kinge; S.J. Honale; C.M. Bobade
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 2: July 2014
Publisher : Institute of Advanced Engineering and Science

The cryptographic algorithms can be implemented with software or built with pure hardware. However Field Programmable Gate Arrays (FPGA) implementation offers quicker solution and can be easily upgraded to incorporate any protocol changes. The available AES algorithm is used for data and it is also suitable for image encryption and decryption to protect the confidential image from an unauthorized access. This project proposes a method in which the image data is an input to AES algorithm, to obtain the encrypted image. and the encrypted image is the input to AES Decryption to get the original image. This project proposed to implement the 128,192 & 256 bit AES algorithm for data encryption and decryption, also to compare the speed of operation, efficiency, security and frequency . The proposed work will be synthesized and simulated on FPGA family of Xilink ISE 13.2 and Modelsim tool respectively in Very high speed integrated circuit Hardware Description Language (VHDL).

Design and Implementation of Adaptive FIR filter using Systolic Architecture Ravi H Bailmare; S.J. Honale; Pravin V Kinge
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 2: July 2014
Publisher : Institute of Advanced Engineering and Science

The tremendous growth of computer and Internet technology wants a data to be process with a high speed and in a powerful manner. In such complex environment, the conventional methods of performing multiplications are not suitable to obtain the perfect solution. To obtain perfect solution parallel computing is use in contradiction. The DLMS adaptive algorithm minimizes approximately the mean square error by recursively altering the weight vector at each sampling instance. In order to obtain minimum mean square error and updated value of weight vector effectively, systolic architecture is used. Systolic architecture is an arrangement of processor where data flows synchronously across array element. This project demonstrates an effective design for adaptive filter using Systolic architecture for DLMS algorithm, synthesized and simulated on Xilinx ISE Project navigator tool in very high speed integrated circuit hardware description language (VHDL) and Field Programmable Gate Arrays (FPGAs). Here, by combining the concept of pipelining and parallel processing in to the systolic architecture the computing speed increases.

Design and Development of ARM9 Evaluation Kit for Embedded Applications Nikhil Alex Thomas; Sanket Dessai; S.G. ShivaPrasad Yadav; Shilpa Chaudhari
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 2: July 2014
Publisher : Institute of Advanced Engineering and Science

In contrast with low end microprocessor, ARM9 core is quite a sophisticated processor. The Evaluation kit plays an important role in the prototype development and verification of the system design before taking to its actual system development hence it’s provide better confidence to the designer. In this paper a project for the Evaluation kit has been designed for embedded system engineer to implement and confirm the functionality of their operating systems which could lead to a comfortable deployment. The independent modules for the interfaces of the ARM9 processor have been designed and the schematics have been developed using OrCAD. From the tested schematics designed in OrCAD, the related PCB is designed using CADSTAR. An eight-layer board is designed for its signal integrity and complexity of the schematic designed. The designed PCB layer is then calibrated and Gerber files are then made and passed on the PCB board manufacturer for PCB fabrication. The PCB board made is then tested for interconnection continuity using multi-meter as the components are loaded on to the board.

FPGA based Multichannel Bit Error Rate Tester for Spacecraft Data Acquisition System Manoj Kumar A; R V Nadagouda; R Jegan
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 2: July 2014
Publisher : Institute of Advanced Engineering and Science

Bit Error Rate (BER) is a principle measure of data transmission link performance. BER tester (BERT) consists of a Pattern Generator and an Analyzer that can be set to the same pattern. The payload data transmitted from the spacecraft consists of one, two or three channels per carrier based on the modulation scheme. The traditional equipments can do BER analysis for only one channel at a time. In order to support multichannel BER analysis, a Personal Computer (PC) based system is designed and implemented in Altera Stratix II (EP2S130F1508C5N) FPGA. Ethernet is configured using WIZnet 5300 (Ethernet Controller) and it is used for communication between FPGA and PC with an application. Application is used to transmit the Pattern Generator’s configurations from PC to FPGA and to receive Analyzer’s status. Packet processing is done for this communication using User Datagram protocol (UDP). On the whole, traditional equipments are replaced by the designed and implemented bit error rate tester.

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