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International Journal of Reconfigurable and Embedded Systems (IJRES)

IJRES
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Published by Institute of Advanced Engineering and Science

ISSN : 20894864 EISSN : 27222608 DOI : -

Core Subject : Economy,

Economics, Econometrics & Finance

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.

Arjuna Subject : -

Articles 5 Documents

Search results for , issue "Vol 3, No 3: November 2014" : 5 Documents clear

Design and Implementation of an Ethernet MAC IP Core for Embedded Applications Sanket Suresh Naik Dessai
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 3: November 2014
Publisher : Institute of Advanced Engineering and Science

An IP (intellectual property) core is a block of logic or data that is used in making a field programmable gate array (FPGA) or application-specific integrated circuit (ASIC) for a product. As essential elements of design reuse, IP cores are part of the growing electronic design automation (EDA) industry trend towards repeated use of previously designed components. Ethernet continues to be one of the most popular LAN technologies. Due to the robustness resulting from its wide acceptance and deployment, there has been an attempt to build Ethernet-based real-time control networks for manufacturing automation. There is a growing demand for low cost, power efficient MAC IP Core for various embedded applications. In this paper a project is discussed to design an Ethernet MAC IP Core solution for such embedded applications. The proposed 10_100_1000 Mbps tri-mode Ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed to use less than 2000 LCs/LEs to implement full function. It will use inferred RAMs and PADs to reduce technology dependence. To increase the flexibility, three optional modules can be added to or removed from the project. A GUI configuration interface, created by Tcl/tk script language, is convenient for configuring optional modules, FIFO depth and verification parameters. Furthermore, a verification system was designed with Tcl/tk user interface, by which the stimulus can be generated automatically and the output packets can be verified with CRC-32 checksum. A solution which would consume a smaller part of the targeted FPGA, and thus giving room for other on-chip peripherals or enable the use of a smaller sized FPGA. To employ a smaller FPGA is desirable since it would reduce power consumption and device price.

Implementation of LOCO-I Lossless Image Compression Algorithm for Deep Space Applications Praveena, P.
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 3: November 2014
Publisher : Institute of Advanced Engineering and Science

Present emerging trend in space science applications is to explore and utilize the deep space. Image coding in deep space communications play vital role in deep space missions. Lossless image compression has been recommended for space science exploration missions to retain the quality of image. On-board memory and bandwidth requirement is reduced by image compression. Programmable logic like field programmable gate array (FPGA) offers an attractive solution for performance and flexibility required by real time image compression algorithms. The powerful feature of FPGA is parallel processing which allows the data to process quicker than microprocessor implementation. This paper elaborates on implementing low complexity lossless image compression algorithm coder on FPGA with minimum utilization of onboard resources for deep space applications.

Bilinear Interpolation Image Scaling Processor for VLSI Architecure Pawar Ashwini Dilip; K Rameshbabu; Kanase Prajakta Ashok; Shital Arjun Shivdas
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 3: November 2014
Publisher : Institute of Advanced Engineering and Science

We introduce image scaling processor using VLSI technique. It consist of Bilinear interpolation, clamp filter and a sharpening spatial filter. Bilinear interpolation algorithm is popular due to its computational efficiency and image quality. But resultant image consist of blurring edges and aliasing artifacts after scaling. To reduce the blurring and aliasing artifacts sharpening spatial filter and clamp filters are used as pre-filter. These filters are realized by using T-model and inversed T-model convolution kernels. To reduce the memory buffer and computing resources for proposed image processor design two T-model or inversed T-model filters are combined into combined filter which requires only one line buffer memory. Also, to reduce hardware cost Reconfigurable calculation unit (RCU)is invented. The VLSI architecture in this work can achieve 280 MHz with 6.08-K gate counts, and its core area is 30 378 μm2 synthesized by a 0.13-μm CMOS process.

Design of AES Pipelined Architecture for Image Encryption/Decryption Module Pravin V. Kinge; S.J. Honale; C.M. Bobade
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 3: November 2014
Publisher : Institute of Advanced Engineering and Science

The relentless growth of Internet and communication technologies has made the extensive use of images unavoidable. The specific characteristics of image like high transmission rate with limited bandwidth, redundancy, bulk capacity and correlation among pixels makes standard algorithms not suitable for image encryption. In order to overcome these limitations for real time applications, design of new algorithms that require less computational power while preserving a sufficient level of security has always been a subject of interest. Here Advanced Encryption Standard (AES),as the most widely used encryption algorithm in many security applications. AES standard has different key size variants, where longer bit keys provide more secure ciphered text output. The available AES algorithm is used for data and it is also suitable for image encryption and decryption to protect the confidential image from an unauthorized access. This project proposes a method in which the image data is an input to Pipelined AES algorithm through Textio, to obtain the encrypted image. and the encrypted image is the input to Pipelined AES Decryption to get the original image. This project proposed to implement the 128,192 & 256 bit Pipelined AES algorithm for image encryption and decryption, also to compare the latency , efficiency, security, frequency & throughput . The proposed work will be synthesized and simulated on FPGA family of Xilink ISE 13.2 and Modelsim tool respectively in Very high speed integrated circuit Hardware Description Language.

Development of Wireless Sensor Network for Traffic Monitoring Systems Sanket Suresh Naik Dessai
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 3: November 2014
Publisher : Institute of Advanced Engineering and Science

Traffic congestion has been a major problem on roads around the world. In addition, there is increase in volume of traffic vehicle density at a steady rate. Thus traffic on major roads has to be controlled to keep the traffic flowing at an acceptable rate. Several schemes for replacing the predominantly used Round Robin (RR) scheme for reducing congestion at traffic junctions have been proposed. Dynamic traffic control schemes adapt to the changing traffic by monitoring the state (such as the number queued up on each lane.). These need appropriate sensing and monitoring systems. In this paper a traffic monitoring and control system based on AMR (Anistropic Magneto Resistive) vehicle sensors, wireless sensor network and a proiritised Weighted Round Robin (WRR) scheduling technique, is developed.AMR sensors installed in road pavement detect the number of vehicles waiting in a traffic lane. The AMR sensors are connected to the master controller to form a Zigbee based sensor network. The master node consists of an ARM processor integrated with a Zigbee masternode. The traffic control algorithm is implemented at master node which is responsible for taking traffic signaling decision. It receives sensor data from all the lanes. A two level priority algorithm with weighted round robin scheduling, where first and second maximum weighted lane are to pass the signal is developed, To avoid starving the least loaded lanes, a cycle of normal round robin scheduling is performed after four rounds of proiritised weighted round robin schedule. The proposed algorithm is simulated and compared with the standard round robin algorithm. The developed algorithm decreases the average waiting time for a commuter while maintaining the average throughput up to average loads. The development traffic monitoring system is successfully demonstrated for a four lane junction.

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