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International Journal of Reconfigurable and Embedded Systems (IJRES)

IJRES
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Published by Institute of Advanced Engineering and Science

ISSN : 20894864 EISSN : 27222608 DOI : -

Core Subject : Economy,

Economics, Econometrics & Finance

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.

Arjuna Subject : -

Articles 8 Documents

Search results for , issue "Vol 5, No 3: November 2016" : 8 Documents clear

Digitalized Electronic Voting System Dukka Bindu Venkata Raghav; Sunith Kumar Bandi
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 3: November 2016
Publisher : Institute of Advanced Engineering and Science

In the present scenario, Electronic Voting Machines ("EVM") are being used in India, generally for state elections. These EVMs are being used since 1999 upto till date. The EVMs reduce the time for both casting a vote and declaring the results when compared to the old paper ballot systems, up to 2004 there is no Tampering and security provided for EVMs after 2004 Supreme court and Election Commission decided to introduce EVMs with Voter Verified Paper Audit Trail(VVPAT) system but it also having some difficulties like missing of names in the voter list, requirement of huge manpower, storing of EVMs for counting purpose etc, so our proposed method is useful to overcome above problems in the voting system by using the Biometric and Aadhaar information.

Design and Development of ARM based Electronic Test Evaluation System for RTO Shweta Salokhe; U. L. Bombale
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 3: November 2016
Publisher : Institute of Advanced Engineering and Science

Electronic test evaluation system for driving license is very useful now a days, as there is increase in the human intervention in the system. This system make the driving license procedure transparent to human being. The proposed technological solution is advancement towards the automation of system and improves the driving test accuracy. As a contribution to society this system reduces the number of road accidents occurs due to untrained drivers.

Hardware Implementation of Intrusion Detection System for Ad-Hoc Network Reji Mano; P.C. Kishore Raja; Christeena Joseph; Radhika Baskar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 3: November 2016
Publisher : Institute of Advanced Engineering and Science

New technologies have been developed in wireless adhoc network need more security. To widespread the adhoc networks we turn in the attention of wireless hand held device mobile phones communicate with short distance using wireless lan card or Bluetooth. The performance of mobile phone are improved greatly for last few years .so security is more important for mobile networks In this paper hardware implementation of single hop ad-hoc network is implemented and analysed using microcontroller. The protocol implemented in this paper is primarily based on, Ad hoc On-Demand Distance Vector routing. We adopt On Demand Distance Vector routing solely based on source routing and “On Demand” process, so each packet does not have to transmit any periodic routing information. We implemented intrusion detection system with five different nodes and the performance parameters like packet delivery ratio, throughput, delay are computed with attacker and without attacker and on demand distance vector routing protocols is proposed to implement in hardware using Zigbee

Design and Implementation of 8x8 Multiplier using 4-2 Compressor and 5-2 Compressor K. Hari Kishore; K. Akhil; G. Viswanath; N. Pavan Kumar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 3: November 2016
Publisher : Institute of Advanced Engineering and Science

In this paper, a 8x8 multiplier is realized by using 4-2 and 5-2 compressors. Low-power high speed 4-2 compressors and 5-2 compressors are extensively utilized for numerical realizations. Both the compressors circuits that is the 4-2 compressor circuit and 5-2 compressor circuit internally consist of the logic gates i.e. the XOR and XNOR gates. 4-2 compressor circuit has been designed uses a brand new partial-product reduction format that consecutively reduces the utmost output new style of number needs less variety of MOSFET’s compared to Wallace Tree Multipliers. The 4-2 compressor used is created from high-speed and consists of logic gates XOR and XNOR gates and transmission gate primarily based electronic device. The regular delay and switching energy also called as power-delay product (PDP) is differentiated with the 5-2 compressor enforced with 4-2 Compressors and while not compressors, and is evidenced to own minimum delay and PDP. Simulations are performed by mistreatment Xilinx ten.1 ISE.

A Gracefully Degrading and Energy-Efﬁcient FPGA Programming using LabVIEW B. Naresh Kumar Reddy; N. Suresh; J.V.N. Ramesh
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 3: November 2016
Publisher : Institute of Advanced Engineering and Science

Programming of Field Programmable Gate Arrays (FPGAs) have long been the domain of engineers with VHDL or Verilog expertise. FPGA’s have caught the attention of algorithm developers and communication researchers, who want to use FPGAs to instantiate systems or implement DSP algorithms. These efforts however, are often stifled by the complexities of programming FPGAs. RTL programming in either VHDL or Verilog is generally not a high level of abstraction needed to represent the world of signal flow graphs and complex signal processing algorithms. This paper describes the FPGA Programs using Graphical Language rather than Verilog, VHDL with the help of LabVIEW and features of the LabVIEW FPGA environment.

FPGA Implementation of Automatic Irrigation and Pesticide Control System D. Hanitha; B. Anusha; M. Durga Prakash
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 3: November 2016
Publisher : Institute of Advanced Engineering and Science

In many parts of the world rainfalls are inadequate to meet agricultural needs of farmers. It thus becomes imperative to use an irrigation system that meets the moisture needs of plants in order to increase food crop production. The system described here monitors the moisture and pesticide control needs of crops. Irrigation control is monitored through suitable moisture sensors and automatically pumps water when the need arises through FPGA control logic thus requiring minimal human interventions. We can also use this system for liquid pesticide supply through the selection. Thus, we achieve the efficient supply of water and pesticide as needed by plants and conserve quantity, energy and time. In this paper, the proposed system is designed using Verilog and implemented on FPGA. The system operation is also explained in DSCH (Digital Schematic) software. The system is very simple to operate and ideally suits the irrigation and pesticide need for green houses as well as farms.

An FPGA Implementation of On Chip UART Testing with BIST Techniques P Bala Gopal; K Hari Kishore
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 3: November 2016
Publisher : Institute of Advanced Engineering and Science

A Universal Asynchronous Receiver Transmitter (UART) is usually implemented for asynchronous serial communication, mostly used for short distance communications. It allows full duplex serial communication link and is used in data communication and control system. Nowadays there is a requirement for on chip testing to overcome the product failures. This paper targets the introduction of Built-in self test (BIST) for UART to overcome the above two constraints of testability and data integrity. The 8-bit UART with BIST module is coded in Verilog HDL and synthesized and simulated using Xilinx XST and implemented on SPARTAN 3E FPGA. Results indicate that this model eliminates the need for expensive testers and thereby it can reduce the development time and cost.

FPGA Based Data Hiding Methods using DNA Cryptography Techniques B. Murali Krishna; CH. Surendra; K. Mani Varma; K. Mani Kanta; S.K. Shabbeer; G.L. Madhumati
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 3: November 2016
Publisher : Institute of Advanced Engineering and Science

To convey the information safely DNA grouping mechanisms are used. There are many methods used by DNA sequences. The proposed method is of both encryption and information concealing utilizing a few properties of Deoxyribonucleic Acid (DNA) groupings. This technique is highlighted that DNA groupings have many more intriguing properties which are used for concealing the information. There are three strategies in this encryption strategy: the Insertion Technique, the Complimentary Pair Technique and the Substitution Strategy .For every single strategy, a specific reference DNA grouping P is chosen and then the taken sequence is changed over with the mystery message M and is consolidated, so that P0 is acquired. P0 is then sent to the collector and the beneficiary can recognize and separate the message M covered up in P. This technique is proposed to utilize INSERTION Strategy. Subsequently, the proposed plan comprises for the most part of two stages. In the principal stage, the mystery information is encoded utilizing a DNA Sequence. In the second stage the encoded information is steganographically covered up into some reference DNA grouping utilizing an insertion strategy. The effectiveness of this security algorithm is seen with many merits and limitations. A, C, G, and T are the 4 nucleotides which are taken for this project.

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