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INDONESIA
Indonesian Journal of Electrical Engineering and Computer Science
Published by Institute of Advanced Engineering and Science
ISSN : 25024752     EISSN : 25024760     DOI : -
Core Subject :
Arjuna Subject : -
Articles 9,199 Documents
 411   412   413   414   415 
The Research of Gray Algorithm and Information Entropy in Route Planning Optimization Ke Zhao
Indonesian Journal of Electrical Engineering and Computer Science Vol 10, No 8: December 2012
Publisher : Institute of Advanced Engineering and Science

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Abstract

In order to solve the Unmanned Aerial Vehicle (UAV) 3-d track planning problems, according to UAV flight are subject to different threats, UAV flight track was established optimal decision-making system, and the fuel consumption, radar threats, missile threats, anti-aircraft threats and atmosphere threats are determined as the evaluation index of objective function, and optimal mathematical model of UAV flight track is constructed. Experience evaluation method is often used to Weight calculation, but there is certain subjectivity .Therefore information entropy method is adopted to determine the Weights by the set of track plans. Grey incidence analysis method is applied to deal with the gray correlation information between the various indicators and to solve the model. Finally, the optimal model is used to scheme selection for flight track planning problem with four threat radar points, five missile threat points, six artillery threat points and four climate threat points to the threat point of flight track planning scheme options. And get the flight track with the best overall performance and Minimum Comprehensive cost, the research provides a theoretical basis for further studying the three-dimensional UAV flight track optimization. DOI: http://dx.doi.org/10.11591/telkomnika.v10i8.1635
Robust Centralized Fusion Kalman Filters with Uncertain Noise Variances Wen-juan Qi; Peng Zhang; Zi-li Deng
Indonesian Journal of Electrical Engineering and Computer Science Vol 12, No 6: June 2014
Publisher : Institute of Advanced Engineering and Science

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Abstract

This paper studies the problem of the designing the robust local and centralized fusion Kalman filters for multisensor system with uncertain noise variances. Using the minimax robust estimation principle, the centralized fusion robust time-varying Kalman filters are presented based on the worst-case conservative system with the conservative upper bound of noise variances. A Lyapunov approach is proposed for the robustness analysis and their robust accuracy relations are proved. It is proved that the robust accuracy of robust centralized fuser is higher than those of robust local Kalman filters. Specially, the corresponding steady-state robust local and centralized fusion Kalman filters are also proposed and the convergence in a realization between time-varying and steady-state Kalman filters is proved by the dynamic error system analysis (DESA) method and dynamic variance error system analysis (DVESA) method. A Monte-Carlo simulation example shows the robustness and accuracy relations. DOI : http://dx.doi.org/10.11591/telkomnika.v12i6.5490
A Power-Gating Scheme for MOS Current Mode Logic Circuits Kaiyu Zou; Jianping Hu
Indonesian Journal of Electrical Engineering and Computer Science Vol 11, No 10: October 2013
Publisher : Institute of Advanced Engineering and Science

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Abstract

MOS Current-Mode Logic (MCML) is widely used for high-speed circuits. However, the MCML circuits have large static power consumptions due to their constant operation currents. This paper presents a power-gating scheme for MCML circuits to reduce their static power dissipations in sleep mode. The PMOS transistors for linear load resistors of MCML circuits are used for power-gating switches. A power-gating control circuit consisting of NMOS and PMOS transistors is added for switching power-gating switches under the control of the sleep signal. The structure and operation of the proposed power-gating scheme are presented. In order to verify the correctness of the proposed power-gating scheme, several basic cells and a full-adder based on MCML circuits are realized. All the circuits are simulated with HSPICE at SMIC 130nm technology. The simulation results show that the power dissipations of the MCML circuits can be greatly reduced by shutting down their idle logic blocks. DOI: http://dx.doi.org/10.11591/telkomnika.v11i10.2877
Reversible logic in pipelined low power vedic multiplier Ansiya Eshack; S. Krishnakumar
Indonesian Journal of Electrical Engineering and Computer Science Vol 16, No 3: December 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v16.i3.pp1265-1272

Abstract

With an ever growing demand for low-power devices, it is a general trend to search for ways to reduce the power consumption of a system. Multipliers are an important requirement in applications linked to Digital Signal Processing, Communication Systems, Optical Computing, Nanotechnology, Low-Power Very Large Scale Integration and Quantum Computing. Conventional mathematics makes multiplication a very long and time consuming process. The use of Vedic mathematics has led to great reduction in the time required for such calculations. The excessive use of Urdhava Tiryakbhyam sutra in multiplication surely proves its effectiveness and simplicity in this domain. This sutra supports the process of pipelining, a method employed in reduction of the power used by a system. Reversible logic has been gaining demand due to its low-power capabilities and is currently being used in many computing applications. The paper proposes two multiplier systems: one design employs the Urdhava Tiryakbhyam sutra along with pipelining and the second uses reversible logic gates into the first design. These proposed systems provide very less delay for result computation and low hardware utilization when compared to non-pipelined Vedic multipliers.
Checkpoint and Replication Oriented Fault Tolerant Mechanism for MapReduce Framework Yang Liu; Wei Wei; Yuhong Zhang
Indonesian Journal of Electrical Engineering and Computer Science Vol 12, No 2: February 2014
Publisher : Institute of Advanced Engineering and Science

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Abstract

MapReduce is an emerging programming paradigm and an associated implementation for processing and generating big data which has been widely applied in data-intensive systems. In cloud environment, node and task failure is no longer accidental but a common feature of large-scale systems. In MapReduce framework, although the rescheduling based fault-tolerant method is simple to implement, it failed to fully consider the location of distributed data, the computation and storage overhead. Thus, a single node failure will increase the completion time dramatically. In this paper, a Checkpoint and Replication Oriented Fault Tolerant scheduling algorithm (CROFT) is proposed, which takes both task and node failure into consideration. Preliminary experiments show that with less storage and network overhead.CROFT will significantly reduce the completion time at failure time, and the overall performance of MapReduce can be improved at least over 30% than original mechanism in Hadoop. DOI : http://dx.doi.org/10.11591/telkomnika.v12i2.4324  
Linear Analysis for Performance of Dual Mass Flywheel with Centrifugal Pendulum Vibration Absorbers System Guangming Zhao; Zhengfeng Jiang; Lei Chen
Indonesian Journal of Electrical Engineering and Computer Science Vol 11, No 5: May 2013
Publisher : Institute of Advanced Engineering and Science

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Abstract

In this study we have offered an investigation of DMF-CPVAs setup for isolating torsional vibration from engine. The simplified mathematical model of DMF-CPVAs setup is built based on the linear theory, the performance of the setup is analyzed, and the result shows that using CPVAs on the DMF leads to an advantage of isolation vibration, instead of just damping vibrations at a specific frequency, could dampen vibrations over a range of frequencies. DOI: http://dx.doi.org/10.11591/telkomnika.v11i5.2462
Improving the Dielectric Properties of High Density Polyethylene by Incorporating Clay-Nano Filler Osama Elsayed Gouda; Sohair F. Mahmoud; Ahmed A. El-Gendy; Ahmed S. Haiba
Indonesian Journal of Electrical Engineering and Computer Science Vol 12, No 12: December 2014
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v12.i12.pp7987-7995

Abstract

Polymer Nano composites have been used for various important industrial applications. The preparation of high density polyethylene composed with Na-montmorillonite Nano filler using melt compounding method for different concentrations of clay-Nano filler of 0%, 2%, 6%, 10%, and 15% has been successfully done. The morphology of the obtained samples was optimized and characterized by scanning electron microscope showing the formation of the polymer Nano composites. The thermal stability and dielectric properties were measured for the prepared samples. Thermal gravimetric analysis results show that thermal stability in polymer Nano composites is more than that in the base polymer. It has been shown that the polymer Nano composites exhibit some very different dielectric characteristics when compared to the base polymer. The dielectric breakdown strength is enhanced by the addition of clay-Nano filler. The dielectric constant and dissipation factor have been studied in the frequency range 200 Hz to 2 MHz at room temperature indicating that enhancements have been occurred in dielectric constant and dissipation factor by the addition of clay-Nano filler in the polymer material when compared with the pure material.
Dynamic keys generation for internet of things Omar Sapti Guma'a; Qasim Mohammed Hussein; Ziyad Tariq Mustafa Al-Ta'i
Indonesian Journal of Electrical Engineering and Computer Science Vol 18, No 2: May 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v18.i2.pp1066-1073

Abstract

In several aspects, interest in IoT has become considerable by researchers and academics in recent years. Data security becomes one of the important challenges facing development of IoT environment. Many algorithms were proposed to secure the IoT applications. The traditional public key cryptographic are inappropriate because it requires high computational. Therefore, lattice-based public-key cryptosystem (LB-PKC) is a favorable technique for IoT security. NTRU is one of a LB-PKC that based on truncated polynomial ring, it has good features, which make it to be an effective alternative to the RSA and ECC algorithms. But, there is LLL algorithm can success to attack it under certain conditions. This paper proposes modifications to NTRU public key cryptosystem to be secure against the lattice-based attack by using LLL algorithm, as well as a method for generating a new keys sequence dynamically. The results from simulations show that the performance of these modifications gives more secure from NTRU. 
Dual DC Motor Speed Control Based on Two Independent Digital PWM Signals using PIC16F877A Microcontroller Ayman Y. Yousef; M. H. Mostafa
Indonesian Journal of Electrical Engineering and Computer Science Vol 2, No 3: June 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v2.i3.pp592-606

Abstract

In this paper a dual open loop speed control system based on two independent PWM signals of small permanent magnet DC (PMDC) motors using PIC16F877A microcontroller (MCU) has been designed and implemented. The Capture/Compare/PWM (CCP) modules of the MCU are configured as PWM mode and the MCU is programmed using flowcode software package to generate two PWM signals with various duty cycles at the same frequency. A dual H-bridge channel chip SN754410 is used to drive the motors. The variation of PWM duty cycles is related directly to controlling the DC motors terminal voltage which directly proportional with speed of each motor. The complete PWM control system model has been simulated using proteus design suite software package. The development of hardware and software of the dual DC motor speed control system has been explained and clarified.
Architecture Design of the Cladding Part Modeling System Yang Junru; Sun Hong; Zhang Lili; Zhang Daozhong; Zhang Yuekan
Indonesian Journal of Electrical Engineering and Computer Science Vol 11, No 9: September 2013
Publisher : Institute of Advanced Engineering and Science

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Abstract

The cladding part is a new type of layered heterogeneous material part with three layers of the substrate, the interface and the clad. According to the part unique material composition and structural characteristic, based on the hierarchical modeling method, the software architecture design of the cladding part modeling system was researched. Using UML (Unified Modeling Language) and the software Rational Rose, the use cases, static logic, dynamic logic and physical deployment of the modeling system were described with the use case diagram, class diagrams, communication diagrams, components diagram and deployment diagram. The research results can guide the development process of the cladding part modeling system with high stability and reliability. DOI: http://dx.doi.org/10.11591/telkomnika.v11i9.3274

Page 413 of 920 | Total Record : 9199

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